From 97f4eb8cfb97c7c5b158e3c0df4611efbf50f403 Mon Sep 17 00:00:00 2001 From: Nick Thompson Date: Sat, 12 Dec 2009 12:12:26 -0500 Subject: Davinci: Configurable NAND chip selects Davinci: Configurable NAND chip selects Add a CONFIG_SYS_NAND_CS setting to all davinci configs and use it to setup the NAND controller in the davinci_nand mtd driver. Signed-off-by: Nick Thompson --- drivers/mtd/nand/davinci_nand.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 41a95685f..1ad802a61 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -82,26 +82,20 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { - int dummy; + u_int32_t val; - dummy = emif_regs->NANDF1ECC; + (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2])); - /* FIXME: only chipselect 0 is supported for now */ - emif_regs->NANDFCR |= 1 << 8; + val = readl(&emif_regs->NANDFCR); + val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); + writel(val, &emif_regs->NANDFCR); } static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) { u_int32_t ecc = 0; - if (region == 1) - ecc = emif_regs->NANDF1ECC; - else if (region == 2) - ecc = emif_regs->NANDF2ECC; - else if (region == 3) - ecc = emif_regs->NANDF3ECC; - else if (region == 4) - ecc = emif_regs->NANDF4ECC; + ecc = readl(&(emif_regs->NANDFECC[region - 1])); return(ecc); } @@ -223,8 +217,11 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) * Start a new ECC calculation for reading or writing 512 bytes * of data. */ - val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12); - emif_regs->NANDFCR = val; + val = readl(&emif_regs->NANDFCR); + val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; + val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_4BIT_ECC_START; + writel(val, &emif_regs->NANDFCR); break; case NAND_ECC_READSYN: val = emif_regs->NAND4BITECC1; -- cgit v1.2.3 From 26be2c53d671ecfd3e0483f0870649ac28322293 Mon Sep 17 00:00:00 2001 From: Nick Thompson Date: Sat, 12 Dec 2009 12:13:10 -0500 Subject: Davinci: NAND enable ECC even when not in NAND boot mode Davinci: NAND enable ECC even when not in NAND boot mode On Davinci platforms, the default NAND device is enabled (for ECC) in low level boot code when NAND boot mode is used. If booting in another mode, NAND ECC is not enabled. The driver should make sure ECC is enabled regardless of boot mode if NAND is configured in U-Boot. Signed-off-by: Nick Thompson --- drivers/mtd/nand/davinci_nand.c | 2 ++ include/asm-arm/arch-davinci/emif_defs.h | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 1ad802a61..90e038e87 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -87,6 +87,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2])); val = readl(&emif_regs->NANDFCR); + val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); writel(val, &emif_regs->NANDFCR); } @@ -219,6 +220,7 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) */ val = readl(&emif_regs->NANDFCR); val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; + val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_4BIT_ECC_START; writel(val, &emif_regs->NANDFCR); diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h index d67292f4b..8fd4e01b8 100644 --- a/include/asm-arm/arch-davinci/emif_defs.h +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -66,11 +66,10 @@ typedef struct { typedef emif_registers *emifregs; +#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) - #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) - #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) -- cgit v1.2.3