From 7b1f1399e876587e0a268a5a471dd444bfbc3114 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:39 -0400 Subject: sbc8548: delete unused MPC8548CDS info carried over from port There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them. Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed. Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/configs/sbc8548.h | 9 --------- 1 file changed, 9 deletions(-) (limited to 'include/configs/sbc8548.h') diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 838b4db9a..3d05afbba 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -42,7 +42,6 @@ #undef CONFIG_PCI1 /* PCI controller 1 */ #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO -#undef CONFIG_PCI2 #undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -343,14 +342,6 @@ #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif -#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif - #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -- cgit v1.2.3 From 9b3ba24f18900633a394416cc056c44a1a6eb754 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:41 -0400 Subject: sbc8548: enable access to second bank of flash The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot. The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/tlb.c | 28 ++++++++++++++++++++++++---- include/configs/sbc8548.h | 8 +++++--- 2 files changed, 29 insertions(+), 7 deletions(-) (limited to 'include/configs/sbc8548.h') diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index ddcb532ee..a0b4e36e7 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -45,13 +45,15 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_4K, 0), /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff800000 16M TLB for 8MB FLASH + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 56M 8MB -> 64MB of user flash + * 0xff800000 8M boot FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000, + CONFIG_SYS_ALT_FLASH + 0x800000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), + 0, 0, BOOKE_PAGESZ_64M, 1), /* * TLB 1: 256M Non-cacheable, guarded @@ -107,6 +109,24 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 7: 4M Non-cacheable, guarded + * 0xfb800000 4M 1st 4MB block of 64MB user FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_4M, 1), + + /* + * TLB 8: 4M Non-cacheable, guarded + * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, + CONFIG_SYS_ALT_FLASH + 0x400000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_4M, 1), + }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 3d05afbba..5c1411f66 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -163,6 +163,7 @@ */ #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ +#define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ #define CONFIG_SYS_BR0_PRELIM 0xff800801 @@ -171,9 +172,10 @@ #define CONFIG_SYS_OR0_PRELIM 0xff806e65 #define CONFIG_SYS_OR6_PRELIM 0xf8006e65 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_ALT_FLASH} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -- cgit v1.2.3 From 11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:04 -0400 Subject: sbc8548: correct local bus SDRAM size from 64M to 128M The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 8 +++++++- board/sbc8548/tlb.c | 23 ++++++++++++++++------- include/configs/sbc8548.h | 42 ++++++++++++++++++++++++++++++++++++++---- 3 files changed, 61 insertions(+), 12 deletions(-) (limited to 'include/configs/sbc8548.h') diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index ce998e1c2..f4bfd925a 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -149,7 +149,7 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) +#if defined(CONFIG_SYS_LBC_SDRAM_SIZE) uint idx; volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); @@ -169,6 +169,12 @@ sdram_init(void) out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); asm("msync"); + out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM); + asm("msync"); + + out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM); + asm("msync"); + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); asm("msync"); diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index a0b4e36e7..a1795fcfb 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -93,14 +93,23 @@ struct fsl_e_tlb_entry tlb_table[] = { /* * TLB 5: 64M Cacheable, non-guarded - * 0xf0000000 64M LBC SDRAM + * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_64M, 1), /* - * TLB 6: 16M Cacheable, non-guarded + * TLB 6: 64M Cacheable, non-guarded + * 0xf4000000 64M LBC SDRAM Second half + */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, + CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -108,24 +117,24 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), + 0, 7, BOOKE_PAGESZ_16M, 1), /* - * TLB 7: 4M Non-cacheable, guarded + * TLB 8: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_4M, 1), + 0, 8, BOOKE_PAGESZ_4M, 1), /* - * TLB 8: 4M Non-cacheable, guarded + * TLB 9: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 9, BOOKE_PAGESZ_4M, 1), }; diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 5c1411f66..009931df5 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -197,13 +197,13 @@ #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 /* - * SDRAM on the Local Bus + * SDRAM on the Local Bus (CS3 and CS4) */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ /* - * Base Register 3 and Option Register 3 configure SDRAM. + * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR3, need: @@ -221,7 +221,7 @@ #define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR3, need: * 64MB mask for AM, OR3[0:7] = 1111 1100 @@ -236,6 +236,40 @@ #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 +/* + * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. + * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. + * + * For BR4, need: + * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 + * + */ + +#define CONFIG_SYS_BR4_PRELIM 0xf4001861 + +/* + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR4, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 + #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -- cgit v1.2.3 From fdc7eb90b504daa020f290604d50da8f7cb70d8a Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:05 -0400 Subject: sbc8548: update PCI/PCI-e support code The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match the latest codebase and makes use of the new shared PCI functions to reduce board duplication. It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB. Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place) Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/law.c | 12 ++++- board/sbc8548/sbc8548.c | 129 ++++++++++++++-------------------------------- board/sbc8548/tlb.c | 53 +++++++++---------- include/configs/sbc8548.h | 45 ++++++++-------- 4 files changed, 96 insertions(+), 143 deletions(-) (limited to 'include/configs/sbc8548.h') diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index e8c7ae2a2..6d1efc0c6 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -32,8 +32,10 @@ * * 0x0000_0000 0x0fff_ffff DDR 256M * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe200_0000 0xe27f_ffff PCI1 IO 8M + * 0xe280_0000 0xe2ff_ffff PCIe IO 8M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf8b0_0000 0xf80f_ffff EEPROM 1M * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M @@ -48,8 +50,14 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif +#ifdef CONFIG_SYS_PCI1_MEM_PHYS SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), +#endif +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index f4bfd925a..194f6ab96 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -321,125 +321,74 @@ static struct pci_controller pci1_hose; static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ -int first_free_busno=0; +#ifdef CONFIG_PCI void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[2]; + u32 devdisr, pordevsr, porpllsr, io_sel; + int first_free_busno = 0; + int num = 0; -#ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; +#ifdef CONFIG_PCIE1 + int pcie_configured; +#endif - uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ + debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); + +#ifdef CONFIG_PCI1 + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; + uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ - if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { printf (" PCI host: %d bit, %s MHz, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33000000) ? "33" : (pci_speed == 66000000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", - pci_arb ? "arbiter" : "external-arbiter" - ); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); -#ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { - /* PCI-X init */ - if (CONFIG_SYS_CLK_FREQ < 66000000) - printf("PCI-X will only work at 66 MHz\n"); - - reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ - | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; - pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); - } -#endif + pci_arb ? "arbiter" : "external-arbiter"); + + SET_STD_PCI_INFO(pci_info[num], 1); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif - gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable PCI2 */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - struct pci_region *r = hose->regions; - - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE at base address %x", - (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); - - first_free_busno=hose->last_busno+1; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + printf (" PCIE at base address %lx\n", pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf (" PCIE: disabled\n"); } - } + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif - } +#endif int board_eth_init(bd_t *bis) { diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index a1795fcfb..38bdeb37c 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -56,60 +56,53 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_64M, 1), /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half + * TLB 1: 1G Non-cacheable, guarded + * 0x80000000 512M PCI1 MEM + * 0xa0000000 512M PCIe MEM */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), + 0, 1, BOOKE_PAGESZ_1G, 1), /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Cacheable, non-guarded + * TLB 2: 256M Cacheable, non-guarded * 0x0 256M DDR SDRAM */ - #if !defined(CONFIG_SPD_EEPROM) +#if !defined(CONFIG_SPD_EEPROM) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 3, BOOKE_PAGESZ_256M, 1), - #endif + 0, 2, BOOKE_PAGESZ_256M, 1), +#endif /* - * TLB 4: 64M Non-cacheable, guarded + * TLB 3: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR - * 0xe2000000 16M PCI1 IO + * 0xe2000000 8M PCI1 IO + * 0xe2800000 8M PCIe IO */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_64M, 1), + 0, 3, BOOKE_PAGESZ_64M, 1), /* - * TLB 5: 64M Cacheable, non-guarded + * TLB 4: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_64M, 1), + 0, 4, BOOKE_PAGESZ_64M, 1), /* - * TLB 6: 64M Cacheable, non-guarded + * TLB 5: 64M Cacheable, non-guarded * 0xf4000000 64M LBC SDRAM Second half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), + 0, 5, BOOKE_PAGESZ_64M, 1), /* - * TLB 7: 16M Cacheable, non-guarded + * TLB 6: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -117,24 +110,24 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16M, 1), + 0, 6, BOOKE_PAGESZ_16M, 1), /* - * TLB 8: 4M Non-cacheable, guarded + * TLB 7: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 7, BOOKE_PAGESZ_4M, 1), /* - * TLB 9: 4M Non-cacheable, guarded + * TLB 8: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_4M, 1), + 0, 8, BOOKE_PAGESZ_4M, 1), }; diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 009931df5..1f340ed7f 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -42,7 +42,14 @@ #undef CONFIG_PCI1 /* PCI controller 1 */ #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO -#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ + +#ifdef CONFIG_PCI +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif +#ifdef CONFIG_PCIE1 +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#endif #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -343,31 +350,27 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ -#endif +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ #endif #ifdef CONFIG_RIO @@ -386,7 +389,7 @@ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -- cgit v1.2.3 From 2738bc8df65ec905094d83f62f87fed123a03b9c Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:06 -0400 Subject: sbc8548: allow enabling PCI via a make config option Prior to this commit, to enable PCI, you had to go manually edit the board config header, and if you had 33MHz PCI, you had to manually change CONFIG_SYS_NS16550_CLK too, which was not real user friendly, This adds the typical PCI and clock speed make targets to the toplevel Makefile in accordance with what is being done with other boards (i.e. using the "-t" to mkconfig). Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- MAKEALL | 4 ++++ Makefile | 8 ++++++-- include/configs/sbc8548.h | 43 +++++++++++++++++++++++++++++++++---------- 3 files changed, 43 insertions(+), 12 deletions(-) (limited to 'include/configs/sbc8548.h') diff --git a/MAKEALL b/MAKEALL index 1d50c3430..b394adbef 100755 --- a/MAKEALL +++ b/MAKEALL @@ -399,6 +399,10 @@ LIST_85xx=" \ PM856 \ sbc8540 \ sbc8548 \ + sbc8548_PCI_33 \ + sbc8548_PCI_66 \ + sbc8548_PCI_33_PCIE \ + sbc8548_PCI_66_PCIE \ sbc8560 \ socrates \ stxgp3 \ diff --git a/Makefile b/Makefile index d8daa8950..55ee25d8a 100644 --- a/Makefile +++ b/Makefile @@ -2544,8 +2544,12 @@ sbc8540_66_config: unconfig fi @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560 -sbc8548_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548 +sbc8548_config \ +sbc8548_PCI_33_config \ +sbc8548_PCI_66_config \ +sbc8548_PCI_33_PCIE_config \ +sbc8548_PCI_66_PCIE_config: unconfig + @$(MKCONFIG) -t $(@:_config=) sbc8548 ppc mpc85xx sbc8548 sbc8560_config \ sbc8560_33_config \ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 1f340ed7f..d10792a22 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Wind River Systems + * Copyright 2007,2009 Wind River Systems * Copyright 2007 Embedded Specialties, Inc. * Copyright 2004, 2007 Freescale Semiconductor. * @@ -24,23 +24,40 @@ /* * sbc8548 board configuration file - * - * Please refer to doc/README.sbc85xx for more info. - * + * Please refer to doc/README.sbc8548 for more info. */ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_PCI +#define CONFIG_PCI +#define CONFIG_PCI1 +#endif + +#ifdef CONFIG_MK_66 +#define CONFIG_SYS_CLK_DIV 1 +#endif + +#ifdef CONFIG_MK_33 +#define CONFIG_SYS_CLK_DIV 2 +#endif + +#ifdef CONFIG_MK_PCIE +#define CONFIG_PCIE1 +#endif + +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_SBC8548 1 /* SBC8548 board specific */ -#undef CONFIG_PCI /* enable any pci type devices */ -#undef CONFIG_PCI1 /* PCI controller 1 */ -#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO #ifdef CONFIG_PCI @@ -58,7 +75,13 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ +/* + * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] + */ +#ifndef CONFIG_SYS_CLK_DIV +#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ +#endif +#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) /* * These can be toggled for performance analysis, otherwise use default. @@ -316,7 +339,7 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 400000000 /* get_bus_freq(0) */ +#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -- cgit v1.2.3