From 899620c2d66d4eef3b2a0034d062e71d45d886c9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 15 Aug 2006 14:22:35 +0200 Subject: Add initial support for the ALPR board from Prodrive NAND needs some additional testing Patch by Heiko Schocher, 15 Aug 2006 --- include/configs/alpr.h | 393 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 393 insertions(+) create mode 100644 include/configs/alpr.h (limited to 'include/configs') diff --git a/include/configs/alpr.h b/include/configs/alpr.h new file mode 100644 index 000000000..eeafcd611 --- /dev/null +++ b/include/configs/alpr.h @@ -0,0 +1,393 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_ALPR 1 /* Board is ebony */ +#define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + + +#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK +#define CONFIG_BAUDRATE 115200 +#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#if 0 /* test-only */ +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. + * The DS1743 code assumes this condition (i.e. -- it assumes the base + * address for the RTC registers is: + * + * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ +#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ +#undef CONFIG_SDRAM_ECC /* enable ECC support */ +#define CFG_SDRAM_TABLE { \ + {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ + {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (PCF8594C) + *----------------------------------------------------------------------*/ +#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ + /* 8 byte page write mode using */ + /* last 3 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=alpr\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/alpr/uImage\0" \ + "kernel_addr=fff00000\0" \ + "ramdisk_addr=fff10000\0" \ + "load=tftp 100000 /tftpboot/alpr/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */ +#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */ +#define CONFIG_PHY2_ADDR 0x00 /* test-only: will be changed */ +#define CONFIG_PHY3_ADDR 0x01 /* PHY address for EMAC3 */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_88E1111_CLK_DELAY 1 /* set CLK delay on ALPR */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#if 0 /* test-only */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_FPGA | \ + CFG_CMD_NAND | \ + CFG_CMD_REGINFO) +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/*----------------------------------------------------------------------- + * FPGA stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_FPGA CFG_ALTERA_CYCLON2 +#undef CFG_FPGA_CHECK_CTRLC +#undef CFG_FPGA_PROG_FEEDBACK +#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in + Reihe geschaltet -> sollte gehen, + aufpassen mit Datasize ist jetzt + halt doppelt so gross ... Seite 306 + ist das mit den multiple Device in PS + Mode erklaert ...*/ + + +/* FPGA program pin configuration */ +#define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ +#define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */ +#define CFG_GPIO_STATUS 20 /* FPGA status pin (cpu input) */ +#define CFG_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */ +#define CFG_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */ + +#define CFG_GPIO_SEL_DPR 14 /* cpu output */ +#define CFG_GPIO_SEL_AVR 15 /* cpu output */ +#define CFG_GPIO_PROG_EN 23 /* cpu output */ + +/* + * NAND-FLASH stuff + */ +#define CFG_MAX_NAND_DEVICE 2 +#define NAND_MAX_CHIPS 2 +#define CFG_NAND_BASE 0x50000000 /* NAND FLASH Base Address */ + +#if 0 +#define CONFIG_MTD_DEBUG +#define CONFIG_MTD_DEBUG_VERBOSE 4 +#endif + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ +/* Memory Bank 1 (NAND-FLASH) initialization */ +/*#define CFG_EBC_PB1AP 0x108f4380 */ /* TODO */ +/*#define CFG_EBC_PB1AP 0x7f854380 */ /* TODO */ +/*#define CFG_EBC_PB1AP 0x108553c0 */ +/*#define CFG_EBC_PB1AP 0x108053c0 */ +#define CFG_EBC_PB1AP 0x10810180 + +/*#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) *//* BS=1MB,BU=R/W,BW=8bit */ +#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ -- cgit v1.2.3 From f3443867e90d2979a7dd1c65b0d537777e1f9850 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 7 Oct 2006 11:30:52 +0200 Subject: Add CONFIG_BOARD_RESET to configure board specific reset function Patch by Stefan Roese, 07 Oct 2006 --- CHANGELOG | 3 +++ board/amcc/yellowstone/yellowstone.c | 6 ++++++ board/amcc/yosemite/yosemite.c | 6 ++++++ cpu/ppc4xx/cpu.c | 20 ++++++++------------ include/configs/yellowstone.h | 1 + include/configs/yosemite.h | 1 + 6 files changed, 25 insertions(+), 12 deletions(-) (limited to 'include/configs') diff --git a/CHANGELOG b/CHANGELOG index e5fa93bc0..4af02002a 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Add CONFIG_BOARD_RESET to configure board specific reset function + Patch by Stefan Roese, 07 Oct 2006 + * Remove compile warnings in fpga code Patch by Stefan Roese, 18 Sep 2006 diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c index 92dc9d4c0..754ae449c 100644 --- a/board/amcc/yellowstone/yellowstone.c +++ b/board/amcc/yellowstone/yellowstone.c @@ -552,3 +552,9 @@ void hw_watchdog_reset(void) } #endif + +void board_reset(void) +{ + /* give reset to BCSR */ + *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09; +} diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 7f2e71820..588ee900d 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -548,3 +548,9 @@ void hw_watchdog_reset(void) } #endif + +void board_reset(void) +{ + /* give reset to BCSR */ + *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09; +} diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 94478dbb1..4e81ce240 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -41,6 +41,10 @@ DECLARE_GLOBAL_DATA_PTR; #endif +#if defined(CONFIG_BOARD_RESET) +void board_reset(void); +#endif + #if defined(CONFIG_440) #define FREQ_EBC (sys_info.freqEPB) #else @@ -414,23 +418,15 @@ int ppc440spe_revB() { int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE) - /*give reset to BCSR*/ - *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09; - +#if defined(CONFIG_BOARD_RESET) + board_reset(); #else - /* * Initiate system reset in debug control register DBCR */ - __asm__ __volatile__("lis 3, 0x3000" ::: "r3"); -#if defined(CONFIG_440) - __asm__ __volatile__("mtspr 0x134, 3"); -#else - __asm__ __volatile__("mtspr 0x3f2, 3"); -#endif + mtspr(dbcr0, 0x30000000); +#endif /* defined(CONFIG_BOARD_RESET) */ -#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/ return 1; } diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index ba27f37f6..58717f8a6 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -37,6 +37,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_BOARD_RESET 1 /* call board_reset() */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 3d7b4a2f4..6e942abca 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -37,6 +37,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_BOARD_RESET 1 /* call board_reset() */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the -- cgit v1.2.3 From 5bc528fa4da751d472397b308137238a6465afd2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 7 Oct 2006 11:35:25 +0200 Subject: Update ALPR code (NAND support working now) Patch by Stefan Roese, 07 Oct 2006 --- CHANGELOG | 3 + board/prodrive/alpr/Makefile | 2 +- board/prodrive/alpr/alpr.c | 31 +++---- board/prodrive/alpr/flash.c | 70 +++++++++++++++ board/prodrive/alpr/init.S | 89 +++++++++---------- board/prodrive/alpr/nand.c | 202 +++++++++++------------------------------- board/prodrive/common/flash.c | 4 + include/configs/alpr.h | 101 +++++++-------------- 8 files changed, 218 insertions(+), 284 deletions(-) create mode 100644 board/prodrive/alpr/flash.c (limited to 'include/configs') diff --git a/CHANGELOG b/CHANGELOG index 7ed5e668f..a21526b97 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Update ALPR code (NAND support working now) + Patch by Stefan Roese, 07 Oct 2006 + * Remove compile warnings in fpga code Patch by Stefan Roese, 07 Oct 2006 diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile index 993ad1995..1024a41a0 100644 --- a/board/prodrive/alpr/Makefile +++ b/board/prodrive/alpr/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o fpga.o nand.o +COBJS = $(BOARD).o flash.o fpga.o nand.o SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 4f250c4f2..e8435bf63 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -38,11 +38,19 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ +#if 0 mtebc(xbcfg, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); +#else + mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | + EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | + EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | + EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); +#endif /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -230,19 +238,6 @@ int is_pci_host(struct pci_controller *hose) #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { - unsigned short temp_short; -#if 0 - /*--------------------------------------------------------------------------+ - | Write the PowerPC440 PCI Configuration regs. - | Enable PowerPC440 to be a master on the PCI bus (PMM). - | Enable PowerPC440 to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -#endif -#if 1 /*--------------------------------------------------------------------------+ | PowerPC440 PCI Master configuration. | Map PLB/processor addresses to PCI memory space. @@ -265,8 +260,6 @@ void pci_master_init(struct pci_controller *hose) out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ - -#endif } #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ @@ -281,3 +274,11 @@ int post_hotkeys_pressed(void) return (ctrlc()); } #endif + +void board_reset(void) +{ + /* + * Initiate chip reset in debug control register DBCR + */ + mtspr(dbcr0, 0x20000000); +} diff --git a/board/prodrive/alpr/flash.c b/board/prodrive/alpr/flash.c new file mode 100644 index 000000000..8fa008430 --- /dev/null +++ b/board/prodrive/alpr/flash.c @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/* + * Prototypes + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); + +unsigned long flash_init(void) +{ + unsigned long size; + int i; + + /* Init: no FLASHes known */ + for (i=0; i -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ #include #include @@ -27,15 +28,15 @@ #define TLB_VALID 0x00000200 /* Supported page sizes */ - #define SZ_1K 0x00000000 #define SZ_4K 0x00000010 #define SZ_16K 0x00000020 #define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 +#define SZ_256K 0x00000040 #define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 #define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 +#define SZ_256M 0x00000090 /* Storage attributes */ #define SA_W 0x00000800 /* Write-through */ @@ -81,29 +82,23 @@ * *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab + .section .bootpg,"ax" + .globl tlbtab tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - - /* PCI */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) -#if 1 - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) -#endif -#if 0 - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 3, AC_R|AC_W|SA_G|SA_I ) -#endif - - /* NAND */ - tlbentry( CFG_NAND_BASE, SZ_16M, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbtab_end + tlbtab_start + tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) + + /* NAND */ + tlbentry( CFG_NAND_BASE, SZ_4K, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbtab_end diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index bd9ba3560..20a809830 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -2,6 +2,9 @@ * (C) Copyright 2006 * Heiko Schocher, DENX Software Engineering, hs@denx.de * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * * See file CREDITS for list of people who contributed to this * project. * @@ -22,69 +25,27 @@ */ #include -#include #if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include #include -#if 0 -#define HS_printf(fmt,arg...) \ - printf("HS %s %s: " fmt,__FILE__, __FUNCTION__, ##arg) -#else -#define HS_printf(fmt,arg...) \ - do { } while (0) -#endif - -#if 0 -#define CPLD_REG uchar -#else -#define CPLD_REG u16 -#endif - struct alpr_ndfc_regs { - CPLD_REG cmd[4]; - CPLD_REG addr_wait; - CPLD_REG term; - CPLD_REG dummy; - uchar dum2[2]; - CPLD_REG data; + u16 cmd[4]; + u16 addr_wait; + u16 term; + u16 dummy; + u16 dummy2; + u16 data; }; static u8 hwctl; -static struct alpr_ndfc_regs *alpr_ndfc; -static int alpr_chip = 0; +static struct alpr_ndfc_regs *alpr_ndfc = NULL; -#if 1 -static int pdnb3_nand_dev_ready(struct mtd_info *mtd); +#define readb(addr) (u8)(*(volatile u16 *)(addr)) +#define writeb(d,addr) *(volatile u16 *)(addr) = ((u16)(d)) -#if 1 -static u_char alpr_read (void *padr) { - return (u_char )*((u16 *)(padr)); -} -#else -static u_char alpr_read (void *padr) { - u16 hilf; - u_char ret = 0; - hilf = *((u16 *)(padr)); - ret = hilf; -printf("%p hilf: %x ret: %x\n", padr, hilf, ret); - return ret; -} -#endif - -static void alpr_write (u_char byte, void *padr) { -HS_printf("%p Byte: %x\n", padr, byte); - *(volatile u16 *)padr = (u16)(byte); -} - -#elif 0 -#define alpr_read(a) (*(volatile u16 *) (a)) -#define alpr_write(a, b) ((*(volatile u16 *) (a)) = (b)) -#else -#define alpr_read(a) readw(a) -#define alpr_write(a, b) writew(a, b) -#endif /* * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to * the NAND devices. The NDFC has command, address and data registers that @@ -93,11 +54,10 @@ HS_printf("%p Byte: %x\n", padr, byte); * We can then use this information in the read and write functions to * determine which NDFC register to access. * - * There are 2 NAND devices on the board, a Hynix HY27US08561A (32 MByte). + * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte). */ -static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd) +static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd) { -HS_printf("cmd: %x\n", cmd); switch (cmd) { case NAND_CTL_SETCLE: hwctl |= 0x1; @@ -114,136 +74,84 @@ HS_printf("cmd: %x\n", cmd); case NAND_CTL_SETNCE: break; case NAND_CTL_CLRNCE: - alpr_write(0x00, &(alpr_ndfc->term)); + writeb(0x00, &(alpr_ndfc->term)); break; } } -static void pdnb3_nand_write_byte(struct mtd_info *mtd, u_char byte) +static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte) { -HS_printf("hwctl: %x %x %x %x\n", hwctl, byte, &(alpr_ndfc->cmd[alpr_chip]), &(alpr_ndfc->addr_wait)); + struct nand_chip *nand = mtd->priv; + if (hwctl & 0x1) - alpr_write(byte, &(alpr_ndfc->cmd[alpr_chip])); + /* + * IO_ADDR_W used as CMD[i] reg to support multiple NAND + * chips. + */ + writeb(byte, nand->IO_ADDR_W); else if (hwctl & 0x2) { - alpr_write(byte, &(alpr_ndfc->addr_wait)); + writeb(byte, &(alpr_ndfc->addr_wait)); } else - alpr_write(byte, &(alpr_ndfc->data)); + writeb(byte, &(alpr_ndfc->data)); } -static u_char pdnb3_nand_read_byte(struct mtd_info *mtd) +static u_char alpr_nand_read_byte(struct mtd_info *mtd) { - return alpr_read(&(alpr_ndfc->data)); + return readb(&(alpr_ndfc->data)); } -static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) { + struct nand_chip *nand = mtd->priv; int i; -/*printf("%s chip:%d hwctl:%x size:%d\n", __FUNCTION__, alpr_chip, hwctl, len);*/ for (i = 0; i < len; i++) { if (hwctl & 0x1) - alpr_write(buf[i], &(alpr_ndfc->cmd[alpr_chip])); - else if (hwctl & 0x2) { - alpr_write(buf[i], &(alpr_ndfc->addr_wait)); - } else { - alpr_write(buf[i], &(alpr_ndfc->data)); - /*printf("i: %d\n", i);*/ - } + /* + * IO_ADDR_W used as CMD[i] reg to support multiple NAND + * chips. + */ + writeb(buf[i], nand->IO_ADDR_W); + else if (hwctl & 0x2) + writeb(buf[i], &(alpr_ndfc->addr_wait)); + else + writeb(buf[i], &(alpr_ndfc->data)); } } -static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) { int i; for (i = 0; i < len; i++) { - buf[i] = alpr_read(&(alpr_ndfc->data)); + buf[i] = readb(&(alpr_ndfc->data)); } } -static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) { int i; for (i = 0; i < len; i++) - if (buf[i] != alpr_read(&(alpr_ndfc->data))) + if (buf[i] != readb(&(alpr_ndfc->data))) return i; return 0; } -static int pdnb3_nand_dev_ready(struct mtd_info *mtd) +static int alpr_nand_dev_ready(struct mtd_info *mtd) { -#if 1 volatile u_char val; -/*printf("%s aufruf\n", __FUNCTION__);*/ /* * Blocking read to wait for NAND to be ready */ - val = alpr_read(&(alpr_ndfc->addr_wait)); + val = readb(&(alpr_ndfc->addr_wait)); /* * Return always true */ return 1; -#else - u8 hwctl_org = hwctl; - unsigned long timeo; - u8 val; - - hwctl = 0x01; - pdnb3_nand_write_byte (mtd, NAND_CMD_STATUS); - hwctl = hwctl_org; - - reset_timer(); - while (1) { - if (get_timer(0) > timeo) { - printf("Timeout!"); - return 0; - } - -val = pdnb3_nand_read_byte(mtd); -/*printf("%s val: %x\n", __FUNCTION__, val);*/ - if (val & NAND_STATUS_READY) - break; - } - return 1; -#endif - -} - -static void alpr_select_chip(struct mtd_info *mtd, int chip) -{ - alpr_chip = chip; -} - -static int alpr_nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) -{ - unsigned long timeo; - - if (state == FL_ERASING) - timeo = CFG_HZ * 400; - else - timeo = CFG_HZ * 20; - - if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) - this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); - else - this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); - - reset_timer(); - - while (1) { - if (get_timer(0) > timeo) { - printf("Timeout!"); - return 0; - } - - if (this->read_byte(mtd) & NAND_STATUS_READY) - break; - } - return this->read_byte(mtd); } void board_nand_init(struct nand_chip *nand) @@ -252,20 +160,14 @@ void board_nand_init(struct nand_chip *nand) nand->eccmode = NAND_ECC_SOFT; - /* Set address of NAND IO lines (Using Linear Data Access Region) */ - nand->IO_ADDR_R = (void __iomem *) ((ulong) alpr_ndfc + 0x10); - nand->IO_ADDR_W = (void __iomem *) ((ulong) alpr_ndfc + 0x10); /* Reference hardware control function */ - nand->hwcontrol = pdnb3_nand_hwcontrol; + nand->hwcontrol = alpr_nand_hwcontrol; /* Set command delay time */ - nand->hwcontrol = pdnb3_nand_hwcontrol; - nand->write_byte = pdnb3_nand_write_byte; - nand->read_byte = pdnb3_nand_read_byte; - nand->write_buf = pdnb3_nand_write_buf; - nand->read_buf = pdnb3_nand_read_buf; - nand->verify_buf = pdnb3_nand_verify_buf; - nand->dev_ready = pdnb3_nand_dev_ready; - nand->select_chip = alpr_select_chip; - nand->waitfunc = alpr_nand_wait; + nand->write_byte = alpr_nand_write_byte; + nand->read_byte = alpr_nand_read_byte; + nand->write_buf = alpr_nand_write_buf; + nand->read_buf = alpr_nand_read_buf; + nand->verify_buf = alpr_nand_verify_buf; + nand->dev_ready = alpr_nand_dev_ready; } #endif diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c index 8630cc166..363631fd8 100644 --- a/board/prodrive/common/flash.c +++ b/board/prodrive/common/flash.c @@ -48,6 +48,7 @@ void flash_print_info(flash_info_t *info) case FLASH_MAN_AMD: printf ("AMD "); break; case FLASH_MAN_FUJ: printf ("FUJITSU "); break; case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("ST "); break; case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; default: printf ("Unknown Vendor "); break; } @@ -156,6 +157,9 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; + case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; diff --git a/include/configs/alpr.h b/include/configs/alpr.h index eeafcd611..c6731ba4d 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -31,8 +31,9 @@ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_BOARD_RESET 1 /* call board_reset() */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CONFIG_SYS_CLK_FREQ 33333000 /* external freq to pll */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -80,45 +81,29 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -/*----------------------------------------------------------------------- - * Environment - *----------------------------------------------------------------------*/ -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#if 0 /* test-only */ -/*----------------------------------------------------------------------- - * NVRAM/RTC - * - * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. - * The DS1743 code assumes this condition (i.e. -- it assumes the base - * address for the RTC registers is: - * - * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - * - *----------------------------------------------------------------------*/ -#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ -#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ -#endif - /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ +#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ +#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ +#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ +/* + * The following defines are added for buggy IOP480 byte interface. + * All other boards should use the standard values (CPCI405 etc.) + */ +#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ +#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ +#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ @@ -177,7 +162,7 @@ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ "flash_nfs=run nfsargs addip addtty;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ @@ -216,24 +201,10 @@ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_88E1111_CLK_DELAY 1 /* set CLK delay on ALPR */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ -#if 0 /* test-only */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) -#else #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ CFG_CMD_DHCP | \ @@ -250,7 +221,6 @@ CFG_CMD_FPGA | \ CFG_CMD_NAND | \ CFG_CMD_REGINFO) -#endif /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -279,15 +249,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- @@ -321,7 +288,6 @@ ist das mit den multiple Device in PS Mode erklaert ...*/ - /* FPGA program pin configuration */ #define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ #define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */ @@ -336,14 +302,12 @@ /* * NAND-FLASH stuff */ -#define CFG_MAX_NAND_DEVICE 2 -#define NAND_MAX_CHIPS 2 -#define CFG_NAND_BASE 0x50000000 /* NAND FLASH Base Address */ - -#if 0 -#define CONFIG_MTD_DEBUG -#define CONFIG_MTD_DEBUG_VERBOSE 4 -#endif +#define CFG_MAX_NAND_DEVICE 4 +#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE +#define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \ + CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 } +#define CFG_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup @@ -353,14 +317,9 @@ /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x92015480 #define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ -/* Memory Bank 1 (NAND-FLASH) initialization */ -/*#define CFG_EBC_PB1AP 0x108f4380 */ /* TODO */ -/*#define CFG_EBC_PB1AP 0x7f854380 */ /* TODO */ -/*#define CFG_EBC_PB1AP 0x108553c0 */ -/*#define CFG_EBC_PB1AP 0x108053c0 */ -#define CFG_EBC_PB1AP 0x10810180 - -/*#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) *//* BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 1 (NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */ #define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ /* -- cgit v1.2.3 From 44a47e6db2694841211f1c8fdbafd36992e9cd1a Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Sat, 11 Nov 2006 22:43:00 +0100 Subject: Change the GPIO pin multiplexing configuration for V38B. The USB GPIO pin group is enabled for USB earlier (in cpu_init_f() instead of usb_lowlevel_init()). --- include/configs/v38b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/v38b.h b/include/configs/v38b.h index cf2d031c9..deabc1761 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -246,7 +246,7 @@ /* * GPIO configuration */ -#define CFG_GPS_PORT_CONFIG 0x90000404 +#define CFG_GPS_PORT_CONFIG 0x90001404 /* * Miscellaneous configurable options -- cgit v1.2.3 From ce3f1a40c507afbab06c5eb58ccdc6713eda3245 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Sat, 11 Nov 2006 22:48:22 +0100 Subject: Disable the watchdog in the default config for the V38B board. --- include/configs/v38b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/v38b.h b/include/configs/v38b.h index deabc1761..554a7a41b 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -34,7 +34,7 @@ #define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ #define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ -#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ +#undef CONFIG_HW_WATCHDOG /* don't use watchdog */ #define CONFIG_NETCONSOLE 1 -- cgit v1.2.3 From 4ef6251403f637841000e0fef9e832aa01339822 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 20 Nov 2006 20:39:52 +0100 Subject: [PATCH] Update AMCC Sequoia config file to support 64MByte NOR FLASH Signed-off-by: Stefan Roese --- include/configs/sequoia.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'include/configs') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 3a76315b4..1a460cde0 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -53,7 +53,7 @@ #define CFG_BOOT_BASE_ADDR 0xf0000000 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ #define CFG_MONITOR_BASE TEXT_BASE #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ #define CFG_OCM_BASE 0xe0010000 /* ocm */ @@ -234,10 +234,10 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ + "rootpath=/opt/eldk/ppc_4xxFP\0" \ "bootfile=/tftpboot/sequoia/uImage\0" \ - "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE180000\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ "load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ "cp.b 100000 FFFA0000 60000\0" \ @@ -378,7 +378,7 @@ #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x03017300 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xba000) +#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) /* Memory Bank 3 (NAND-FLASH) initialization */ #define CFG_EBC_PB3AP 0x018003c0 @@ -387,7 +387,7 @@ #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ /* Memory Bank 3 (NOR-FLASH) initialization */ #define CFG_EBC_PB3AP 0x03017300 -#define CFG_EBC_PB3CR (CFG_FLASH | 0xba000) +#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) /* Memory Bank 0 (NAND-FLASH) initialization */ #define CFG_EBC_PB0AP 0x018003c0 -- cgit v1.2.3 From 78d620ebb5871d252270dedfad60c6568993b780 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 23 Nov 2006 22:58:58 +0100 Subject: Updates for TQM5200 modules: - fix off-by-one error in board/tqm5200/cam5200_flash.c error message - simplify "udate" definitions --- board/tqm5200/cam5200_flash.c | 2 +- board/tqm5200/tqm5200.c | 2 +- include/configs/TQM5200.h | 46 +++++++++++-------------------------------- 3 files changed, 13 insertions(+), 37 deletions(-) (limited to 'include/configs') diff --git a/board/tqm5200/cam5200_flash.c b/board/tqm5200/cam5200_flash.c index 1a40633e5..8c3f62e39 100644 --- a/board/tqm5200/cam5200_flash.c +++ b/board/tqm5200/cam5200_flash.c @@ -759,7 +759,7 @@ unsigned long flash_init(void) if (flash_info[i].flash_id == FLASH_UNKNOWN) { printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); + i+1, size_b[i], size_b[i] << 20); flash_info[i].sector_count = -1; flash_info[i].size = 0; } diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index cb57a5e26..a4322b666 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -289,7 +289,7 @@ int checkboard (void) #elif defined(CONFIG_TB5200) # define CARRIER_NAME "TB5200" #elif defined(CONFIG_CAM5200) -# define CARRIER_NAME "Cam5200" +# define CARRIER_NAME "CAM5200" #elif defined(CONFIG_FO300) # define CARRIER_NAME "FO300" #else diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 4bae103e0..08674ca49 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -217,43 +217,19 @@ #undef CONFIG_BOOTARGS -#ifdef CONFIG_STK52XX -# if defined(CONFIG_TQM5200_B) -# if defined(CFG_LOWBOOT) -# define ENV_UPDT \ - "update=protect off FC000000 FC07FFFF;" \ - "erase FC000000 FC07FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC07FFFF\0" -# else /* highboot */ -# define ENV_UPDT \ - "update=protect off FFF00000 FFF7FFFF;" \ - "erase FFF00000 FFF7FFFF;" \ +#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT) +# define ENV_UPDT \ + "update=protect off FFF00000 +${filesize};" \ + "erase FFF00000 +${filesize};" \ "cp.b 200000 FFF00000 ${filesize};" \ - "protect on FFF00000 FFF7FFFF\0" -# endif /* CFG_LOWBOOT */ -# else /* !CONFIG_TQM5200_B */ -# define ENV_UPDT \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" -# endif /* CONFIG_TQM5200_B */ -#elif defined (CONFIG_CAM5200) -# define ENV_UPDT \ - "update=protect off FC000000 FC03FFFF;" \ - "erase FC000000 FC03FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC03FFFF\0" -#elif defined (CONFIG_FO300) + "protect on FFF00000 +${filesize}\0" +#else /* default lowboot configuration */ # define ENV_UPDT \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ + "update=protect off FC000000 +${filesize};" \ + "erase FC000000 +${filesize};" \ "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" -#else -# error "Unknown Carrier Board" -#endif /* CONFIG_STK52XX */ + "protect on FC000000 +${filesize}\0" +#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -432,7 +408,7 @@ */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ -#if defined(CONFIG_TQM5200_B) +#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) #define CFG_ENV_SECT_SIZE 0x40000 #else #define CFG_ENV_SECT_SIZE 0x20000 -- cgit v1.2.3 From 1c2ce2262069510f31c7d3fd7efd3d58b8c0c148 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 27 Nov 2006 14:12:17 +0100 Subject: [PATCH] Update Prodrive ALPR board support (440GX) Signed-off-by: Stefan Roese --- board/prodrive/alpr/Makefile | 4 +- board/prodrive/alpr/alpr.c | 100 +++++++++++++++++++++++++++++++------------ board/prodrive/alpr/fpga.c | 79 ++++++++++++++++------------------ board/prodrive/alpr/init.S | 1 - board/prodrive/alpr/nand.c | 16 +++---- cpu/ppc4xx/4xx_enet.c | 5 +-- cpu/ppc4xx/cpu.c | 4 +- cpu/ppc4xx/cpu_init.c | 4 ++ include/configs/alpr.h | 96 +++++++++++++++++++---------------------- 9 files changed, 171 insertions(+), 138 deletions(-) (limited to 'include/configs') diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile index 1024a41a0..00dc180bb 100644 --- a/board/prodrive/alpr/Makefile +++ b/board/prodrive/alpr/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o fpga.o nand.o +COBJS = $(BOARD).o fpga.o nand.o SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) @@ -33,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index e8435bf63..238956127 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -26,6 +26,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -33,24 +34,14 @@ extern int alpr_fpga_init(void); int board_early_init_f (void) { - unsigned long mfr; - - /*-------------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------------*/ -#if 0 - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | - EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | - EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); -#else + /*------------------------------------------------------------------------- + * Initialize EBC CONFIG + *-------------------------------------------------------------------------*/ mtebc(xbcfg, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); -#endif /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -58,8 +49,8 @@ int board_early_init_f (void) mtdcr (uic0sr, 0xffffffff); /* clear all */ mtdcr (uic0er, 0x00000000); /* disable all */ mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr (uic0pr, 0xfffffe03); /* per manual */ + mtdcr (uic0tr, 0x01c00000); /* per manual */ mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic0sr, 0xffffffff); /* clear all */ @@ -85,12 +76,57 @@ int board_early_init_f (void) mtdcr (uicb0pr, 0xfc000000); /* */ mtdcr (uicb0tr, 0x00000000); /* */ mtdcr (uicb0vr, 0x00000001); /* */ - mfsdr (sdr_mfr, mfr); - mfr &= ~SDR0_MFR_ECS_MASK; + + /* Setup GPIO/IRQ multiplexing */ + mtsdr(sdr_pfc0, 0x01a03e00); return 0; } +int last_stage_init(void) +{ + unsigned short reg; + + /* + * Configure LED's of both Marvell 88E1111 PHY's + * + * This has to be done after the 4xx ethernet driver is loaded, + * so "last_stage_init()" is the right place. + */ + miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®); + reg |= 0x0001; + miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg); + miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®); + reg |= 0x0001; + miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg); + + return 0; +} + +static int board_rev(void) +{ + int rev; + u32 pfc0; + + /* Setup GPIO14 & 15 as GPIO */ + mfsdr(sdr_pfc0, pfc0); + pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1; + mtsdr(sdr_pfc0, pfc0); + + /* Setup as input */ + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); + + rev = (in32(GPIO0_IR) >> 16) & 0x3; + + /* Setup GPIO14 & 15 as non GPIO again */ + mfsdr(sdr_pfc0, pfc0); + pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1); + mtsdr(sdr_pfc0, pfc0); + + return rev; +} + int checkboard (void) { char *s = getenv ("serial#"); @@ -100,7 +136,7 @@ int checkboard (void) puts (", serial# "); puts (s); } - putc ('\n'); + printf(" (Rev. %d)\n", board_rev()); return (0); } @@ -224,10 +260,26 @@ void pci_target_init(struct pci_controller * hose ) * ************************************************************************/ #if defined(CONFIG_PCI) + +static void wait_for_pci_ready(void) +{ + /* + * Configure EREADY as input + */ + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY); + udelay(1000); + + for (;;) { + if (in32(GPIO0_IR) & CFG_GPIO_EREADY) + return; + } + +} + int is_pci_host(struct pci_controller *hose) { - /* The ocotea board is always configured as host. */ - return(1); + wait_for_pci_ready(); + return 1; /* return 1 for host controller */ } #endif /* defined(CONFIG_PCI) */ @@ -274,11 +326,3 @@ int post_hotkeys_pressed(void) return (ctrlc()); } #endif - -void board_reset(void) -{ - /* - * Initiate chip reset in debug control register DBCR - */ - mtspr(dbcr0, 0x20000000); -} diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c index 78307b486..e94360f81 100644 --- a/board/prodrive/alpr/fpga.c +++ b/board/prodrive/alpr/fpga.c @@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if (CONFIG_FPGA) +#if defined(CONFIG_FPGA) #ifdef FPGA_DEBUG #define PRINTF(fmt,args...) printf (fmt ,##args) @@ -44,46 +44,38 @@ DECLARE_GLOBAL_DATA_PTR; #define PRINTF(fmt,args...) #endif -static unsigned long regval; +static unsigned long regval; -#define SET_GPIO_REG_0(reg, bit) {\ - regval = in32(reg);\ - regval &= ~(0x80000000 >> bit);\ - out32(reg, regval);\ - } - -#define SET_GPIO_REG_1(reg, bit) {\ - regval = in32(reg);\ - regval |= (0x80000000 >> bit);\ - out32(reg, regval);\ - } - -#define GPIO_CLK_PIN 0x00002000 -#define GPIO_CLK_PIN_I 0xffffdfff -#define GPIO_DAT_PIN 0x00001000 -#define GPIO_DAT_PIN_I 0xffffefff -#define GPIO_CLKDAT_PIN_I 0xffffcfff +#define SET_GPIO_REG_0(reg, bit) { \ + regval = in32(reg); \ + regval &= ~(0x80000000 >> bit); \ + out32(reg, regval); \ + } -#define SET_GPIO_CLK_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLK_PIN_I); -#define SET_GPIO_CLK_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_CLK_PIN); -#define SET_GPIO_DAT_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_DAT_PIN_I); -#define SET_GPIO_DAT_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_DAT_PIN); +#define SET_GPIO_REG_1(reg, bit) { \ + regval = in32(reg); \ + regval |= (0x80000000 >> bit); \ + out32(reg, regval); \ + } -#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit) -#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit) +#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit) +#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit) -#define SET_GPIO_CLK_0_Z1 out32(GPIO0_OR, (in32(GPIO0_OR) & GPIO_CLK_PIN_I) | GPIO_DAT_PIN); -#define SET_GPIO_CLK_0_Z0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLKDAT_PIN_I); +#define FPGA_PRG (0x80000000 >> CFG_GPIO_PROG_EN) +#define FPGA_CONFIG (0x80000000 >> CFG_GPIO_CONFIG) +#define FPGA_DATA (0x80000000 >> CFG_GPIO_DATA) +#define FPGA_CLK (0x80000000 >> CFG_GPIO_CLK) +#define OLD_VAL (FPGA_PRG | FPGA_CONFIG) -#define FPGA_WRITE_1 { \ - SET_GPIO_CLK_0_Z1\ - SET_GPIO_CLK_1} +#define SET_FPGA(data) out32(GPIO0_OR, data) -#define FPGA_WRITE_0 { \ - SET_GPIO_CLK_0_Z0\ - SET_GPIO_CLK_1} +#define FPGA_WRITE_1 { \ + SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \ + SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ -#define P_GP(reg) (reg & 0x00023f00) +#define FPGA_WRITE_0 { \ + SET_FPGA(OLD_VAL | 0 | 0 ); /* set data to 0 */ \ + SET_FPGA(OLD_VAL | FPGA_CLK | 0 );} /* set data to 1 */ /* Plattforminitializations */ /* Here we have to set the FPGA Chain */ @@ -102,7 +94,7 @@ int fpga_pre_fn (int cookie) SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR); SET_GPIO_0((CFG_GPIO_SEL_DPR)); - /* initialize the GPIO Pins */ + /* initialize the GPIO Pins */ /* output */ SET_GPIO_0(CFG_GPIO_CLK); SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK); @@ -174,7 +166,7 @@ int fpga_done_fn (int cookie) } /* writes the complete buffer to the FPGA - writing the complete buffer in one function is very faster, + writing the complete buffer in one function is much faster, then calling it for every bit */ int fpga_write_fn (void *buf, size_t len, int flush, int cookie) { @@ -182,14 +174,10 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie) unsigned char *data = (unsigned char *) buf; unsigned char val=0; int i; + int len_40 = len / 40; while (bytecount < len) { -#ifdef CFG_FPGA_CHECK_CTRLC - if (ctrlc ()) { - return FPGA_FAIL; - } -#endif - val = data[bytecount ++ ]; + val = data[bytecount++]; i = 8; do { if (val & 0x01) { @@ -202,8 +190,13 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie) } while (i > 0); #ifdef CFG_FPGA_PROG_FEEDBACK - if (bytecount % (len / 40) == 0) + if (bytecount % len_40 == 0) { putc ('.'); /* let them know we are alive */ +#ifdef CFG_FPGA_CHECK_CTRLC + if (ctrlc ()) + return FPGA_FAIL; +#endif + } #endif } return FPGA_SUCCESS; diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S index 1baa609c0..135674c26 100644 --- a/board/prodrive/alpr/init.S +++ b/board/prodrive/alpr/init.S @@ -34,7 +34,6 @@ #define SZ_64K 0x00000030 #define SZ_256K 0x00000040 #define SZ_1M 0x00000050 -#define SZ_8M 0x00000060 #define SZ_16M 0x00000070 #define SZ_256M 0x00000090 diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index 20a809830..e63c921ef 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -32,19 +32,19 @@ #include struct alpr_ndfc_regs { - u16 cmd[4]; - u16 addr_wait; - u16 term; - u16 dummy; - u16 dummy2; - u16 data; + u8 cmd[4]; + u8 addr_wait; + u8 term; + u8 dummy; + u8 dummy2; + u8 data; }; static u8 hwctl; static struct alpr_ndfc_regs *alpr_ndfc = NULL; -#define readb(addr) (u8)(*(volatile u16 *)(addr)) -#define writeb(d,addr) *(volatile u16 *)(addr) = ((u16)(d)) +#define readb(addr) (u8)(*(volatile u8 *)(addr)) +#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d)) /* * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 81d49ffdf..8c517baf3 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -470,8 +470,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #else if ((devnum == 0) || (devnum == 1)) { out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); - } - else { /* ((devnum == 2) || (devnum == 3)) */ + } else { /* ((devnum == 2) || (devnum == 3)) */ out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | (RGMII_FER_RGMII << RGMII_FER_V (3)))); @@ -808,7 +807,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; hw_p->rx_ready[i] = -1; #if 0 - printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr); + printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr); #endif } diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index faa525750..c45525db0 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -426,8 +426,8 @@ int ppc440spe_revB() { int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#if defined(CONFIG_BOARD_RESET) - board_reset(); +#if defined(CFG_4xx_RESET_TYPE) + mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28); #else /* * Initiate system reset in debug control register DBCR diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index def46f15c..4b746b072 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -320,6 +320,10 @@ cpu_init_f (void) val |= 0xb8000000; /* generate system reset after 1.34 seconds */ #else val |= 0xf0000000; /* generate system reset after 2.684 seconds */ +#endif +#if defined(CFG_4xx_RESET_TYPE) + val &= ~0x30000000; /* clear WRC bits */ + val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */ #endif mtspr(tcr, val); diff --git a/include/configs/alpr.h b/include/configs/alpr.h index c6731ba4d..60da82028 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -31,25 +31,25 @@ #define CONFIG_440GX 1 /* Specifc GX support */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_BOARD_RESET 1 /* call board_reset() */ +#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ -#define CONFIG_SYS_CLK_FREQ 33333000 /* external freq to pll */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */ -#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ -#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ -#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ -#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 #define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) @@ -84,26 +84,13 @@ /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ - +#define CFG_FLASH_CFI 1 /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ -#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ - +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ @@ -154,7 +141,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ + "netdev=eth3\0" \ "hostname=alpr\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ @@ -162,18 +149,19 @@ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \ + "mem=193M\0" \ "flash_nfs=run nfsargs addip addtty;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/alpr/uImage\0" \ + "rootpath=/opt/projects/alpr/nfs_root\0" \ + "bootfile=/alpr/uImage\0" \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ - "load=tftp 100000 /tftpboot/alpr/u-boot.bin\0" \ + "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ @@ -181,7 +169,7 @@ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ #define CONFIG_BAUDRATE 115200 @@ -192,8 +180,8 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */ #define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */ -#define CONFIG_PHY2_ADDR 0x00 /* test-only: will be changed */ -#define CONFIG_PHY3_ADDR 0x01 /* PHY address for EMAC3 */ +#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */ +#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */ #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 @@ -251,9 +239,11 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ /*----------------------------------------------------------------------- * PCI stuff @@ -264,7 +254,7 @@ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ +#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ /* Board-specific PCI */ #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ @@ -276,11 +266,10 @@ /*----------------------------------------------------------------------- * FPGA stuff - *----------------------------------------------------------------------- - */ + *-----------------------------------------------------------------------*/ #define CONFIG_FPGA CFG_ALTERA_CYCLON2 -#undef CFG_FPGA_CHECK_CTRLC -#undef CFG_FPGA_PROG_FEEDBACK +#define CFG_FPGA_CHECK_CTRLC +#define CFG_FPGA_PROG_FEEDBACK #define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in Reihe geschaltet -> sollte gehen, aufpassen mit Datasize ist jetzt @@ -299,9 +288,16 @@ #define CFG_GPIO_SEL_AVR 15 /* cpu output */ #define CFG_GPIO_PROG_EN 23 /* cpu output */ -/* +/*----------------------------------------------------------------------- + * Definitions for GPIO setup + *-----------------------------------------------------------------------*/ +#define CFG_GPIO_EREADY (0x80000000 >> 26) +#define CFG_GPIO_REV0 (0x80000000 >> 14) +#define CFG_GPIO_REV1 (0x80000000 >> 15) + +/*----------------------------------------------------------------------- * NAND-FLASH stuff - */ + *-----------------------------------------------------------------------*/ #define CFG_MAX_NAND_DEVICE 4 #define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE #define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ @@ -320,7 +316,7 @@ /* Memory Bank 1 (NAND-FLASH) initialization */ #define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */ -#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */ +#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ /* * For booting Linux, the board info and command line data @@ -333,9 +329,7 @@ */ #define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions -- cgit v1.2.3 From ec0c2ec725aec9524a177a77ce75559e644a931a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 27 Nov 2006 14:46:06 +0100 Subject: [PATCH] Remove testing 4xx enet PHY setup Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 17 +---------------- include/configs/alpr.h | 2 +- 2 files changed, 2 insertions(+), 17 deletions(-) (limited to 'include/configs') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 8c517baf3..7a2483c3c 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -560,22 +560,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) * otherwise, just check the speeds & feeds */ if (hw_p->first_init == 0) { -#if defined(CONFIG_88E1111_CLK_DELAY) - /* - * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs - * the "RGMII transmit timing control" and "RGMII receive - * timing control" bits set, so that Gbit communication works - * without problems. - * Also set the "Transmitter disable" to 1 to enable the - * transmitter. - * After setting these bits a soft-reset must occur for this - * change to become active. - */ - miiphy_read (dev->name, reg, 0x14, ®_short); - reg_short |= (1 << 7) | (1 << 1) | (1 << 0); - miiphy_write (dev->name, reg, 0x14, reg_short); -#endif -#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */ +#if defined(CONFIG_M88E1111_PHY) miiphy_write (dev->name, reg, 0x14, 0x0ce3); miiphy_write (dev->name, reg, 0x18, 0x4101); miiphy_write (dev->name, reg, 0x09, 0x0e00); diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 60da82028..bbe6b76bf 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -187,7 +187,7 @@ #define CONFIG_HAS_ETH2 #define CONFIG_HAS_ETH3 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_88E1111_CLK_DELAY 1 /* set CLK delay on ALPR */ +#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ -- cgit v1.2.3 From d1a72545296800b7e219f93104ad5836f0003d66 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 27 Nov 2006 17:34:10 +0100 Subject: [PATCH] Select NAND embedded environment from board configuration The current NAND Bootloader setup forces the environment variables to be in line with the bootloader. This change enables the configuration to be made in the board include file instead so that it can be individually enabled. Signed-off-by: Nick Spence Signed-off-by: Stefan Roese --- include/configs/sequoia.h | 1 + include/environment.h | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 1a460cde0..00b92220c 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -102,6 +102,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ #endif /*----------------------------------------------------------------------- diff --git a/include/environment.h b/include/environment.h index 26b07120d..af605ab7a 100644 --- a/include/environment.h +++ b/include/environment.h @@ -79,8 +79,7 @@ # ifdef CFG_ENV_OFFSET_REDUND # define CFG_REDUNDAND_ENVIRONMENT # endif -# if defined(CONFIG_NAND_U_BOOT) -/* Use embedded environment in NAND boot versions */ +# ifdef CFG_ENV_IS_EMBEDDED # define ENV_IS_EMBEDDED 1 # endif #endif /* CFG_ENV_IS_IN_NAND */ -- cgit v1.2.3