From 9acb626fc145e7327f94fd77f927dce08dd978a8 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@pollux.denx.de>
Date: Thu, 20 Apr 2006 08:42:42 +0200
Subject: Add MCF5282 support (without preloader) relocate ichache_State to ram
 u-boot can run from internal flash Add EB+MCF-EV123 board support. Add m68k
 Boards to MAKEALL Patch from Jens Scharsig, 08 Aug 2005

---
 include/asm-m68k/immap_5282.h  |  82 ++++---
 include/asm-m68k/m5282.h       | 529 +++++++++++++++++++++++++++++++++++++++--
 include/configs/EB+MCF-EV123.h | 223 +++++++++++++++++
 3 files changed, 783 insertions(+), 51 deletions(-)
 create mode 100644 include/configs/EB+MCF-EV123.h

(limited to 'include')

diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h
index f2b77db87..a95912f9b 100644
--- a/include/asm-m68k/immap_5282.h
+++ b/include/asm-m68k/immap_5282.h
@@ -25,39 +25,63 @@
 #ifndef __IMMAP_5282__
 #define __IMMAP_5282__
 
+struct sys_ctrl {
+	uint ipsbar;
+	char res1[4];
+	uint rambar;
+	char res2[4];
+	uchar crsr;
+	uchar cwcr;
+	uchar lpicr;
+	uchar cwsr;
+	uint dmareqc;
+	char res3[4];
+	uint mpark;
+
+    /* TODO: finish these */
+};
+
+
 
 /* Fast ethernet controller registers
  */
 typedef struct fec {
-	uint	fec_ecntrl;		/* ethernet control register		*/
-	uint	fec_ievent;		/* interrupt event register		*/
-	uint	fec_imask;		/* interrupt mask register		*/
-	uint	fec_ivec;		/* interrupt level and vector status	*/
-	uint	fec_r_des_active;	/* Rx ring updated flag			*/
-	uint	fec_x_des_active;	/* Tx ring updated flag			*/
-	uint	res3[10];		/* reserved				*/
-	uint	fec_mii_data;		/* MII data register			*/
-	uint	fec_mii_speed;		/* MII speed control register		*/
-	uint	res4[17];		/* reserved				*/
-	uint	fec_r_bound;		/* end of RAM (read-only)		*/
-	uint	fec_r_fstart;		/* Rx FIFO start address		*/
-	uint	res5[6];		/* reserved				*/
-	uint	fec_x_fstart;		/* Tx FIFO start address		*/
-	uint	res7[21];		/* reserved				*/
-	uint	fec_r_cntrl;		/* Rx control register			*/
-	uint	fec_r_hash;		/* Rx hash register			*/
-	uint	res8[14];		/* reserved				*/
-	uint	fec_x_cntrl;		/* Tx control register			*/
-	uint	res9[0x9e];		/* reserved				*/
-	uint	fec_addr_low;		/* lower 32 bits of station address	*/
-	uint	fec_addr_high;		/* upper 16 bits of station address	*/
-	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
-	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
-	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
-	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
-	uint	fec_r_buff_size;	/* Rx buffer size			*/
-	uint	res2[9];		/* reserved				*/
-	uchar	fec_fifo[960];		/* fifo RAM				*/
+	uint    res1;		/* reserved                	1000*/
+	uint    fec_ievent;	/* interrupt event register	1004*/	/* EIR */
+	uint    fec_imask;	/* interrupt mask register	1008*/	/* EIMR */
+	uint    res2;		/* reserved			100c*/
+	uint    fec_r_des_active;    /* Rx ring updated flag	1010*/	/* RDAR */
+	uint    fec_x_des_active;    /* Tx ring updated flag	1014*/	/* XDAR */
+	uint    res3[3];        /* reserved			1018*/
+	uint    fec_ecntrl;	/* ethernet control register	1024*/	/* ECR */
+	uint    res4[6];        /* reserved			1028*/
+	uint    fec_mii_data;	/* MII data register		1040*/	/* MDATA */
+	uint    fec_mii_speed;	/* MII speed control register	1044*/	/* MSCR */
+                                      /*1044*/
+	uint    res5[7];	/* reserved			1048*/
+	uint    fec_mibc;	/* MIB Control/Status register	1064*/ /* MIBC */
+	uint    res6[7];	/* reserved			1068*/
+	uint    fec_r_cntrl;	/* Rx control register		1084*/	/* RCR */
+	uint    res7[15];	/* reserved			1088*/
+	uint    fec_x_cntrl;	/* Tx control register		10C4*/	/* TCR */
+	uint    res8[7];	/* reserved			10C8*/
+	uint    fec_addr_low;	/* lower 32 bits of station address */	/* PALR */
+	uint    fec_addr_high;	/* upper 16 bits of station address  */	/* PAUR */
+	uint    fec_opd;	/* opcode + pause duration	10EC*/	/* OPD */
+	uint    res9[10];	/* reserved			10F0*/
+	uint    fec_ihash_table_high;	/* upper 32-bits of individual hash *//* IAUR */
+	uint    fec_ihash_table_low;	/* lower 32-bits of individual hash  *//* IALR */
+	uint    fec_ghash_table_high;	/* upper 32-bits of group hash  *//* GAUR */
+	uint    fec_ghash_table_low;	/* lower 32-bits of group hash  *//* GALR */
+	uint    res10[7];	/* reserved			1128*/
+	uint    fec_tfwr;	/* Transmit FIFO watermark	1144*/	/* TFWR */
+	uint    res11;		/* reserved			1148*/
+	uint    fec_r_bound;	/* FIFO Receive Bound Register = end of *//* FRBR */
+	uint    fec_r_fstart;	/* FIFO Receive FIfo Start Registers =  *//* FRSR */
+	uint    res12[11];	/* reserved			1154*/
+	uint    fec_r_des_start;/* beginning of Rx descriptor ring    1180*//* ERDSR */
+	uint    fec_x_des_start;/* beginning of Tx descriptor ring    1184*//* ETDSR */
+	uint    fec_r_buff_size;/* Rx buffer size		1188*/	/* EMRBR */
 } fec_t;
 
 #endif /* __IMMAP_5282__ */
diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h
index 073b0bc79..e5058a46a 100644
--- a/include/asm-m68k/m5282.h
+++ b/include/asm-m68k/m5282.h
@@ -1,9 +1,6 @@
 /*
  * mcf5282.h -- Definitions for Motorola Coldfire 5282
  *
- * Based on mcf5282sim.h of uCLinux distribution:
- *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
- *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -34,27 +31,515 @@
 
 #define INT_RAM_SIZE	65536
 
+/* General Purpose I/O Module GPIO */
 
-/*
- *	Define the 5282 SIM register set addresses.
- */
-#define	MCFICM_INTC0		0x0c00		/* Base for Interrupt Ctrl 0 */
-#define	MCFICM_INTC1		0x0d00		/* Base for Interrupt Ctrl 0 */
-#define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
-#define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
-#define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
-#define	MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
-#define	MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
-#define	MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
-#define	MCFINTC_IRLR		0x18		/* */
-#define	MCFINTC_IACKL		0x19		/* */
-#define	MCFINTC_ICR0		0x40		/* Base ICR register */
-
-#define	MCFINT_UART0		13		/* Interrupt number for UART0 */
-#define	MCFINT_PIT1		55		/* Interrupt number for PIT1 */
-
-#define	MCF5282_GPIO_PUAPAR	0x10005C
+#define MCFGPIO_PORTA		(*(vu_char *) (CFG_MBAR+0x100000))
+#define MCFGPIO_PORTB		(*(vu_char *) (CFG_MBAR+0x100001))
+#define MCFGPIO_PORTC		(*(vu_char *) (CFG_MBAR+0x100002))
+#define MCFGPIO_PORTD		(*(vu_char *) (CFG_MBAR+0x100003))
+#define MCFGPIO_PORTE		(*(vu_char *) (CFG_MBAR+0x100004))
+#define MCFGPIO_PORTF		(*(vu_char *) (CFG_MBAR+0x100005))
+#define MCFGPIO_PORTG		(*(vu_char *) (CFG_MBAR+0x100006))
+#define MCFGPIO_PORTH		(*(vu_char *) (CFG_MBAR+0x100007))
+#define MCFGPIO_PORTJ		(*(vu_char *) (CFG_MBAR+0x100008))
+#define MCFGPIO_PORTDD		(*(vu_char *) (CFG_MBAR+0x100009))
+#define MCFGPIO_PORTEH		(*(vu_char *) (CFG_MBAR+0x10000A))
+#define MCFGPIO_PORTEL		(*(vu_char *) (CFG_MBAR+0x10000B))
+#define MCFGPIO_PORTAS		(*(vu_char *) (CFG_MBAR+0x10000C))
+#define MCFGPIO_PORTQS		(*(vu_char *) (CFG_MBAR+0x10000D))
+#define MCFGPIO_PORTSD		(*(vu_char *) (CFG_MBAR+0x10000E))
+#define MCFGPIO_PORTTC		(*(vu_char *) (CFG_MBAR+0x10000F))
+#define MCFGPIO_PORTTD		(*(vu_char *) (CFG_MBAR+0x100010))
+#define MCFGPIO_PORTUA		(*(vu_char *) (CFG_MBAR+0x100011))
+
+#define MCFGPIO_DDRA		(*(vu_char *) (CFG_MBAR+0x100014))
+#define MCFGPIO_DDRB		(*(vu_char *) (CFG_MBAR+0x100015))
+#define MCFGPIO_DDRC		(*(vu_char *) (CFG_MBAR+0x100016))
+#define MCFGPIO_DDRD		(*(vu_char *) (CFG_MBAR+0x100017))
+#define MCFGPIO_DDRE		(*(vu_char *) (CFG_MBAR+0x100018))
+#define MCFGPIO_DDRF		(*(vu_char *) (CFG_MBAR+0x100019))
+#define MCFGPIO_DDRG		(*(vu_char *) (CFG_MBAR+0x10001A))
+#define MCFGPIO_DDRH		(*(vu_char *) (CFG_MBAR+0x10001B))
+#define MCFGPIO_DDRJ		(*(vu_char *) (CFG_MBAR+0x10001C))
+#define MCFGPIO_DDRDD		(*(vu_char *) (CFG_MBAR+0x10001D))
+#define MCFGPIO_DDREH		(*(vu_char *) (CFG_MBAR+0x10001E))
+#define MCFGPIO_DDREL		(*(vu_char *) (CFG_MBAR+0x10001F))
+#define MCFGPIO_DDRAS		(*(vu_char *) (CFG_MBAR+0x100020))
+#define MCFGPIO_DDRQS		(*(vu_char *) (CFG_MBAR+0x100021))
+#define MCFGPIO_DDRSD		(*(vu_char *) (CFG_MBAR+0x100022))
+#define MCFGPIO_DDRTC		(*(vu_char *) (CFG_MBAR+0x100023))
+#define MCFGPIO_DDRTD		(*(vu_char *) (CFG_MBAR+0x100024))
+#define MCFGPIO_DDRUA		(*(vu_char *) (CFG_MBAR+0x100025))
+
+#define MCFGPIO_PORTAP		(*(vu_char *) (CFG_MBAR+0x100028))
+#define MCFGPIO_PORTBP		(*(vu_char *) (CFG_MBAR+0x100029))
+#define MCFGPIO_PORTCP		(*(vu_char *) (CFG_MBAR+0x10002A))
+#define MCFGPIO_PORTDP		(*(vu_char *) (CFG_MBAR+0x10002B))
+#define MCFGPIO_PORTEP		(*(vu_char *) (CFG_MBAR+0x10002C))
+#define MCFGPIO_PORTFP		(*(vu_char *) (CFG_MBAR+0x10002D))
+#define MCFGPIO_PORTGP		(*(vu_char *) (CFG_MBAR+0x10002E))
+#define MCFGPIO_PORTHP		(*(vu_char *) (CFG_MBAR+0x10002F))
+#define MCFGPIO_PORTJP		(*(vu_char *) (CFG_MBAR+0x100030))
+#define MCFGPIO_PORTDDP		(*(vu_char *) (CFG_MBAR+0x100031))
+#define MCFGPIO_PORTEHP		(*(vu_char *) (CFG_MBAR+0x100032))
+#define MCFGPIO_PORTELP		(*(vu_char *) (CFG_MBAR+0x100033))
+#define MCFGPIO_PORTASP		(*(vu_char *) (CFG_MBAR+0x100034))
+#define MCFGPIO_PORTQSP		(*(vu_char *) (CFG_MBAR+0x100035))
+#define MCFGPIO_PORTSDP		(*(vu_char *) (CFG_MBAR+0x100036))
+#define MCFGPIO_PORTTCP		(*(vu_char *) (CFG_MBAR+0x100037))
+#define MCFGPIO_PORTTDP		(*(vu_char *) (CFG_MBAR+0x100038))
+#define MCFGPIO_PORTUAP		(*(vu_char *) (CFG_MBAR+0x100039))
+
+#define MCFGPIO_SETA		(*(vu_char *) (CFG_MBAR+0x100028))
+#define MCFGPIO_SETB		(*(vu_char *) (CFG_MBAR+0x100029))
+#define MCFGPIO_SETC		(*(vu_char *) (CFG_MBAR+0x10002A))
+#define MCFGPIO_SETD		(*(vu_char *) (CFG_MBAR+0x10002B))
+#define MCFGPIO_SETE		(*(vu_char *) (CFG_MBAR+0x10002C))
+#define MCFGPIO_SETF		(*(vu_char *) (CFG_MBAR+0x10002D))
+#define MCFGPIO_SETG   		(*(vu_char *) (CFG_MBAR+0x10002E))
+#define MCFGPIO_SETH   		(*(vu_char *) (CFG_MBAR+0x10002F))
+#define MCFGPIO_SETJ   		(*(vu_char *) (CFG_MBAR+0x100030))
+#define MCFGPIO_SETDD  		(*(vu_char *) (CFG_MBAR+0x100031))
+#define MCFGPIO_SETEH  		(*(vu_char *) (CFG_MBAR+0x100032))
+#define MCFGPIO_SETEL  		(*(vu_char *) (CFG_MBAR+0x100033))
+#define MCFGPIO_SETAS  		(*(vu_char *) (CFG_MBAR+0x100034))
+#define MCFGPIO_SETQS  		(*(vu_char *) (CFG_MBAR+0x100035))
+#define MCFGPIO_SETSD  		(*(vu_char *) (CFG_MBAR+0x100036))
+#define MCFGPIO_SETTC  		(*(vu_char *) (CFG_MBAR+0x100037))
+#define MCFGPIO_SETTD  		(*(vu_char *) (CFG_MBAR+0x100038))
+#define MCFGPIO_SETUA  		(*(vu_char *) (CFG_MBAR+0x100039))
+
+#define MCFGPIO_CLRA  		(*(vu_char *) (CFG_MBAR+0x10003C))
+#define MCFGPIO_CLRB  		(*(vu_char *) (CFG_MBAR+0x10003D))
+#define MCFGPIO_CLRC  		(*(vu_char *) (CFG_MBAR+0x10003E))
+#define MCFGPIO_CLRD  		(*(vu_char *) (CFG_MBAR+0x10003F))
+#define MCFGPIO_CLRE  		(*(vu_char *) (CFG_MBAR+0x100040))
+#define MCFGPIO_CLRF  		(*(vu_char *) (CFG_MBAR+0x100041))
+#define MCFGPIO_CLRG  		(*(vu_char *) (CFG_MBAR+0x100042))
+#define MCFGPIO_CLRH  		(*(vu_char *) (CFG_MBAR+0x100043))
+#define MCFGPIO_CLRJ  		(*(vu_char *) (CFG_MBAR+0x100044))
+#define MCFGPIO_CLRDD  		(*(vu_char *) (CFG_MBAR+0x100045))
+#define MCFGPIO_CLREH  		(*(vu_char *) (CFG_MBAR+0x100046))
+#define MCFGPIO_CLREL  		(*(vu_char *) (CFG_MBAR+0x100047))
+#define MCFGPIO_CLRAS  		(*(vu_char *) (CFG_MBAR+0x100048))
+#define MCFGPIO_CLRQS  		(*(vu_char *) (CFG_MBAR+0x100049))
+#define MCFGPIO_CLRSD  		(*(vu_char *) (CFG_MBAR+0x10004A))
+#define MCFGPIO_CLRTC  		(*(vu_char *) (CFG_MBAR+0x10004B))
+#define MCFGPIO_CLRTD  		(*(vu_char *) (CFG_MBAR+0x10004C))
+#define MCFGPIO_CLRUA  		(*(vu_char *) (CFG_MBAR+0x10004D))
+
+#define MCFGPIO_PBCDPAR  	(*(vu_char *) (CFG_MBAR+0x100050))
+#define MCFGPIO_PFPAR  		(*(vu_char *) (CFG_MBAR+0x100051))
+#define MCFGPIO_PEPAR  		(*(vu_short *)(CFG_MBAR+0x100052))
+#define MCFGPIO_PJPAR  		(*(vu_char *) (CFG_MBAR+0x100054))
+#define MCFGPIO_PSDPAR  	(*(vu_char *) (CFG_MBAR+0x100055))
+#define MCFGPIO_PASPAR  	(*(vu_short *)(CFG_MBAR+0x100056))
+#define MCFGPIO_PEHLPAR  	(*(vu_char *) (CFG_MBAR+0x100058))
+#define MCFGPIO_PQSPAR  	(*(vu_char *) (CFG_MBAR+0x100059))
+#define MCFGPIO_PTCPAR  	(*(vu_char *) (CFG_MBAR+0x10005A))
+#define MCFGPIO_PTDPAR  	(*(vu_char *) (CFG_MBAR+0x10005B))
+#define MCFGPIO_PUAPAR  	(*(vu_char *) (CFG_MBAR+0x10005C))
+
+/* Bit level definitions and macros */
+#define MCFGPIO_PORT7			(0x80)
+#define MCFGPIO_PORT6			(0x40)
+#define MCFGPIO_PORT5			(0x20)
+#define MCFGPIO_PORT4			(0x10)
+#define MCFGPIO_PORT3			(0x08)
+#define MCFGPIO_PORT2			(0x04)
+#define MCFGPIO_PORT1			(0x02)
+#define MCFGPIO_PORT0			(0x01)
+#define MCFGPIO_PORT(x)			(0x01<<x)
+
+#define MCFGPIO_DDR7			(0x80)
+#define MCFGPIO_DDR6			(0x40)
+#define MCFGPIO_DDR5			(0x20)
+#define MCFGPIO_DDR4			(0x10)
+#define MCFGPIO_DDR3			(0x08)
+#define MCFGPIO_DDR2			(0x04)
+#define MCFGPIO_DDR1			(0x02)
+#define MCFGPIO_DDR0			(0x01)
+#define MCFGPIO_DDR(x)			(0x01<<x)
+
+#define MCFGPIO_Px7			(0x80)
+#define MCFGPIO_Px6			(0x40)
+#define MCFGPIO_Px5			(0x20)
+#define MCFGPIO_Px4			(0x10)
+#define MCFGPIO_Px3			(0x08)
+#define MCFGPIO_Px2			(0x04)
+#define MCFGPIO_Px1			(0x02)
+#define MCFGPIO_Px0			(0x01)
+#define MCFGPIO_Px(x)			(0x01<<x)
+
+
+#define MCFGPIO_PBCDPAR_PBPA		(0x80)
+#define MCFGPIO_PBCDPAR_PCDPA		(0x40)
+
+#define MCFGPIO_PEPAR_PEPA7		(0x4000)
+#define MCFGPIO_PEPAR_PEPA6		(0x1000)
+#define MCFGPIO_PEPAR_PEPA5		(0x0400)
+#define MCFGPIO_PEPAR_PEPA4		(0x0100)
+#define MCFGPIO_PEPAR_PEPA3		(0x0040)
+#define MCFGPIO_PEPAR_PEPA2		(0x0010)
+#define MCFGPIO_PEPAR_PEPA1(x)		(((x)&0x3)<<2)
+#define MCFGPIO_PEPAR_PEPA0(x)		(((x)&0x3))
+
+#define MCFGPIO_PFPAR_PFPA7		(0x80)
+#define MCFGPIO_PFPAR_PFPA6		(0x40)
+#define MCFGPIO_PFPAR_PFPA5		(0x20)
+
+#define MCFGPIO_PJPAR_PJPA7		(0x80)
+#define MCFGPIO_PJPAR_PJPA6		(0x40)
+#define MCFGPIO_PJPAR_PJPA5		(0x20)
+#define MCFGPIO_PJPAR_PJPA4		(0x10)
+#define MCFGPIO_PJPAR_PJPA3		(0x08)
+#define MCFGPIO_PJPAR_PJPA2		(0x04)
+#define MCFGPIO_PJPAR_PJPA1		(0x02)
+#define MCFGPIO_PJPAR_PJPA0		(0x01)
+#define MCFGPIO_PJPAR_PJPA(x)		(0x01<<x)
+
+#define MCFGPIO_PSDPAR_PSDPA		(0x80)
+
+#define MCFGPIO_PASPAR_PASPA5(x)	(((x)&0x3)<<10)
+#define MCFGPIO_PASPAR_PASPA4(x)	(((x)&0x3)<<8)
+#define MCFGPIO_PASPAR_PASPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PASPAR_PASPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PASPAR_PASPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PASPAR_PASPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PEHLPAR_PEHPA		(0x80)
+#define MCFGPIO_PEHLPAR_PELPA		(0x40)
+
+#define MCFGPIO_PQSPAR_PQSPA6		(0x40)
+#define MCFGPIO_PQSPAR_PQSPA5		(0x20)
+#define MCFGPIO_PQSPAR_PQSPA4		(0x10)
+#define MCFGPIO_PQSPAR_PQSPA3		(0x08)
+#define MCFGPIO_PQSPAR_PQSPA2		(0x04)
+#define MCFGPIO_PQSPAR_PQSPA1		(0x02)
+#define MCFGPIO_PQSPAR_PQSPA0		(0x01)
+#define MCFGPIO_PQSPAR_PQSPA(x)		(0x01<<x)
+
+#define MCFGPIO_PTCPAR_PTCPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PTCPAR_PTCPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PTCPAR_PTCPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PTCPAR_PTCPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PTDPAR_PTDPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PTDPAR_PTDPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PTDPAR_PTDPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PTDPAR_PTDPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PUAPAR_PUAPA3		(0x08)
+#define MCFGPIO_PUAPAR_PUAPA2		(0x04)
+#define MCFGPIO_PUAPAR_PUAPA1		(0x02)
+#define MCFGPIO_PUAPAR_PUAPA0		(0x01)
+
+/* System Conrol Module SCM */
+
+#define MCFSCM_RAMBAR           (*(vu_long *) (CFG_MBAR+0x00000008))
+#define MCFSCM_CRSR		(*(vu_char *) (CFG_MBAR+0x00000010))
+#define MCFSCM_CWCR		(*(vu_char *) (CFG_MBAR+0x00000011))
+#define MCFSCM_LPICR		(*(vu_char *) (CFG_MBAR+0x00000012))
+#define MCFSCM_CWSR		(*(vu_char *) (CFG_MBAR+0x00000013))
+
+#define MCFSCM_MPARK		(*(vu_long *) (CFG_MBAR+0x0000001C))
+#define MCFSCM_MPR		(*(vu_char *) (CFG_MBAR+0x00000020))
+#define MCFSCM_PACR0		(*(vu_char *) (CFG_MBAR+0x00000024))
+#define MCFSCM_PACR1		(*(vu_char *) (CFG_MBAR+0x00000025))
+#define MCFSCM_PACR2		(*(vu_char *) (CFG_MBAR+0x00000026))
+#define MCFSCM_PACR3		(*(vu_char *) (CFG_MBAR+0x00000027))
+#define MCFSCM_PACR4		(*(vu_char *) (CFG_MBAR+0x00000028))
+#define MCFSCM_PACR5		(*(vu_char *) (CFG_MBAR+0x0000002A))
+#define MCFSCM_PACR6		(*(vu_char *) (CFG_MBAR+0x0000002B))
+#define MCFSCM_PACR7		(*(vu_char *) (CFG_MBAR+0x0000002C))
+#define MCFSCM_PACR8		(*(vu_char *) (CFG_MBAR+0x0000002E))
+#define MCFSCM_GPACR0		(*(vu_char *) (CFG_MBAR+0x00000030))
+#define MCFSCM_GPACR1		(*(vu_char *) (CFG_MBAR+0x00000031))
+
+
+#define MCFSCM_CRSR_EXT		(0x80)
+#define MCFSCM_CRSR_CWDR	(0x20)
+#define MCFSCM_RAMBAR_BA(x)     ((x)&0xFFFF0000)
+#define MCFSCM_RAMBAR_BDE       (0x00000200)
+
+/* Reset Controller Module RCM */
+
+#define MCFRESET_RCR		(*(vu_char *) (CFG_MBAR+0x00110000))
+#define MCFRESET_RSR		(*(vu_char *) (CFG_MBAR+0x00110001))
+
+#define MCFRESET_RCR_SOFTRST    (0x80)
+#define MCFRESET_RCR_FRCRSTOUT  (0x40)
+#define MCFRESET_RCR_LVDF       (0x10)
+#define MCFRESET_RCR_LVDIE      (0x08)
+#define MCFRESET_RCR_LVDRE      (0x04)
+#define MCFRESET_RCR_LVDE       (0x01)
+
+#define MCFRESET_RSR_LVD        (0x40)
+#define MCFRESET_RSR_SOFT       (0x20)
+#define MCFRESET_RSR_WDR        (0x10)
+#define MCFRESET_RSR_POR        (0x08)
+#define MCFRESET_RSR_EXT        (0x04)
+#define MCFRESET_RSR_LOC        (0x02)
+#define MCFRESET_RSR_LOL        (0x01)
+#define MCFRESET_RSR_ALL        (0x7F)
+#define MCFRESET_RCR_SOFTRST    (0x80)
+#define MCFRESET_RCR_FRCRSTOUT  (0x40)
+
+/* Chip Configuration Module CCM */
+
+#define MCFCCM_CCR		(*(vu_short *)(CFG_MBAR+0x00110004))
+#define MCFCCM_RCON		(*(vu_short *)(CFG_MBAR+0x00110008))
+#define MCFCCM_CIR		(*(vu_short *)(CFG_MBAR+0x0011000A))
+
+
+/* Bit level definitions and macros */
+#define MCFCCM_CCR_LOAD			(0x8000)
+#define MCFCCM_CCR_MODE(x) 		(((x)&0x0007)<<8)
+#define MCFCCM_CCR_SZEN    		(0x0040)
+#define MCFCCM_CCR_PSTEN   		(0x0020)
+#define MCFCCM_CCR_BME			(0x0008)
+#define MCFCCM_CCR_BMT(x)  		(((x)&0x0007))
+
+#define MCFCCM_CIR_PIN_MASK		(0xFF00)
+#define MCFCCM_CIR_PRN_MASK		(0x00FF)
+
+/* Clock Module */
+
+#define MCFCLOCK_SYNCR          (*(vu_short *)(CFG_MBAR+0x120000))
+#define MCFCLOCK_SYNSR          (*(vu_char *) (CFG_MBAR+0x120002))
+
+#define MCFCLOCK_SYNCR_MFD(x)   (((x)&0x0007)<<12)
+#define MCFCLOCK_SYNCR_RFD(x)   (((x)&0x0007)<<8)
+#define MCFCLOCK_SYNSR_LOCK     0x08
+
+#define MCFSDRAMC_DCR		(*(vu_short *)(CFG_MBAR+0x00000040))
+#define MCFSDRAMC_DACR0		(*(vu_long *) (CFG_MBAR+0x00000048))
+#define MCFSDRAMC_DMR0		(*(vu_long *) (CFG_MBAR+0x0000004c))
+#define MCFSDRAMC_DACR1		(*(vu_long *) (CFG_MBAR+0x00000050))
+#define MCFSDRAMC_DMR1		(*(vu_long *) (CFG_MBAR+0x00000054))
+
+#define MCFSDRAMC_DCR_NAM	(0x2000)
+#define MCFSDRAMC_DCR_COC	(0x1000)
+#define MCFSDRAMC_DCR_IS	(0x0800)
+#define MCFSDRAMC_DCR_RTIM_3	(0x0000)
+#define MCFSDRAMC_DCR_RTIM_6	(0x0200)
+#define MCFSDRAMC_DCR_RTIM_9	(0x0400)
+#define MCFSDRAMC_DCR_RC(x)	((x)&0x01FF)
+
+#define MCFSDRAMC_DACR_BASE(x)	((x)&0xFFFC0000)
+#define MCFSDRAMC_DACR_RE	(0x00008000)
+#define MCFSDRAMC_DACR_CASL(x)	(((x)&0x03)<<12)
+#define MCFSDRAMC_DACR_CBM(x)	(((x)&0x07)<<8)
+#define MCFSDRAMC_DACR_PS_32	(0x00000000)
+#define MCFSDRAMC_DACR_PS_16	(0x00000020)
+#define MCFSDRAMC_DACR_PS_8	(0x00000010)
+#define MCFSDRAMC_DACR_IP	(0x00000008)
+#define MCFSDRAMC_DACR_IMRS	(0x00000040)
+
+#define MCFSDRAMC_DMR_BAM_16M	(0x00FC0000)
+#define MCFSDRAMC_DMR_WP        (0x00000100)
+#define MCFSDRAMC_DMR_CI        (0x00000040)
+#define MCFSDRAMC_DMR_AM        (0x00000020)
+#define MCFSDRAMC_DMR_SC        (0x00000010)
+#define MCFSDRAMC_DMR_SD        (0x00000008)
+#define MCFSDRAMC_DMR_UC        (0x00000004)
+#define MCFSDRAMC_DMR_UD        (0x00000002)
+#define MCFSDRAMC_DMR_V         (0x00000001)
+
+#define MCFWTM_WCR              (*(vu_short *)(CFG_MBAR+0x00140000))
+#define MCFWTM_WMR              (*(vu_short *)(CFG_MBAR+0x00140002))
+#define MCFWTM_WCNTR            (*(vu_short *)(CFG_MBAR+0x00140004))
+#define MCFWTM_WSR              (*(vu_short *)(CFG_MBAR+0x00140006))
+
+/*  Chip SELECT Module CSM */
+#define MCFCSM_CSAR0		(*(vu_short *)(CFG_MBAR+0x00000080))
+#define MCFCSM_CSMR0		(*(vu_long *) (CFG_MBAR+0x00000084))
+#define MCFCSM_CSCR0		(*(vu_short *)(CFG_MBAR+0x0000008a))
+#define MCFCSM_CSAR1		(*(vu_short *)(CFG_MBAR+0x0000008C))
+#define MCFCSM_CSMR1		(*(vu_long *) (CFG_MBAR+0x00000090))
+#define MCFCSM_CSCR1		(*(vu_short *)(CFG_MBAR+0x00000096))
+#define MCFCSM_CSAR2		(*(vu_short *)(CFG_MBAR+0x00000098))
+#define MCFCSM_CSMR2		(*(vu_long *) (CFG_MBAR+0x0000009C))
+#define MCFCSM_CSCR2		(*(vu_short *)(CFG_MBAR+0x000000A2))
+#define MCFCSM_CSAR3		(*(vu_short *)(CFG_MBAR+0x000000A4))
+#define MCFCSM_CSMR3		(*(vu_long *) (CFG_MBAR+0x000000A8))
+#define MCFCSM_CSCR3		(*(vu_short *)(CFG_MBAR+0x000000AE))
+
+#define MCFCSM_CSMR_BAM(x)	((x) & 0xFFFF0000)
+#define MCFCSM_CSMR_WP		(1<<8)
+#define MCFCSM_CSMR_V		(0x01)
+#define MCFCSM_CSCR_WS(x)	((x & 0x0F)<<10)
+#define MCFCSM_CSCR_AA		(0x0100)
+#define MCFCSM_CSCR_PS_32	(0x0000)
+#define MCFCSM_CSCR_PS_8	(0x0040)
+#define MCFCSM_CSCR_PS_16	(0x0080)
+
+/*********************************************************************
+*
+* General Purpose Timer (GPT) Module
+*
+*********************************************************************/
+
+#define MCFGPTA_GPTIOS		(*(vu_char *)(CFG_MBAR+0x1A0000))
+#define MCFGPTA_GPTCFORC	(*(vu_char *)(CFG_MBAR+0x1A0001))
+#define MCFGPTA_GPTOC3M		(*(vu_char *)(CFG_MBAR+0x1A0002))
+#define MCFGPTA_GPTOC3D		(*(vu_char *)(CFG_MBAR+0x1A0003))
+#define MCFGPTA_GPTCNT		(*(vu_short *)(CFG_MBAR+0x1A0004))
+#define MCFGPTA_GPTSCR1		(*(vu_char *)(CFG_MBAR+0x1A0006))
+#define MCFGPTA_GPTTOV		(*(vu_char *)(CFG_MBAR+0x1A0008))
+#define MCFGPTA_GPTCTL1		(*(vu_char *)(CFG_MBAR+0x1A0009))
+#define MCFGPTA_GPTCTL2		(*(vu_char *)(CFG_MBAR+0x1A000B))
+#define MCFGPTA_GPTIE		(*(vu_char *)(CFG_MBAR+0x1A000C))
+#define MCFGPTA_GPTSCR2		(*(vu_char *)(CFG_MBAR+0x1A000D))
+#define MCFGPTA_GPTFLG1		(*(vu_char *)(CFG_MBAR+0x1A000E))
+#define MCFGPTA_GPTFLG2		(*(vu_char *)(CFG_MBAR+0x1A000F))
+#define MCFGPTA_GPTC0		(*(vu_short *)(CFG_MBAR+0x1A0010))
+#define MCFGPTA_GPTC1		(*(vu_short *)(CFG_MBAR+0x1A0012))
+#define MCFGPTA_GPTC2		(*(vu_short *)(CFG_MBAR+0x1A0014))
+#define MCFGPTA_GPTC3		(*(vu_short *)(CFG_MBAR+0x1A0016))
+#define MCFGPTA_GPTPACTL	(*(vu_char *)(CFG_MBAR+0x1A0018))
+#define MCFGPTA_GPTPAFLG	(*(vu_char *)(CFG_MBAR+0x1A0019))
+#define MCFGPTA_GPTPACNT	(*(vu_short *)(CFG_MBAR+0x1A001A))
+#define MCFGPTA_GPTPORT		(*(vu_char *)(CFG_MBAR+0x1A001D))
+#define MCFGPTA_GPTDDR		(*(vu_char *)(CFG_MBAR+0x1A001E))
+
+
+#define MCFGPTB_GPTIOS		(*(vu_char *)(CFG_MBAR+0x1B0000))
+#define MCFGPTB_GPTCFORC	(*(vu_char *)(CFG_MBAR+0x1B0001))
+#define MCFGPTB_GPTOC3M		(*(vu_char *)(CFG_MBAR+0x1B0002))
+#define MCFGPTB_GPTOC3D		(*(vu_char *)(CFG_MBAR+0x1B0003))
+#define MCFGPTB_GPTCNT		(*(vu_short *)(CFG_MBAR+0x1B0004))
+#define MCFGPTB_GPTSCR1		(*(vu_char *)(CFG_MBAR+0x1B0006))
+#define MCFGPTB_GPTTOV		(*(vu_char *)(CFG_MBAR+0x1B0008))
+#define MCFGPTB_GPTCTL1		(*(vu_char *)(CFG_MBAR+0x1B0009))
+#define MCFGPTB_GPTCTL2		(*(vu_char *)(CFG_MBAR+0x1B000B))
+#define MCFGPTB_GPTIE		(*(vu_char *)(CFG_MBAR+0x1B000C))
+#define MCFGPTB_GPTSCR2		(*(vu_char *)(CFG_MBAR+0x1B000D))
+#define MCFGPTB_GPTFLG1		(*(vu_char *)(CFG_MBAR+0x1B000E))
+#define MCFGPTB_GPTFLG2		(*(vu_char *)(CFG_MBAR+0x1B000F))
+#define MCFGPTB_GPTC0		(*(vu_short *)(CFG_MBAR+0x1B0010))
+#define MCFGPTB_GPTC1		(*(vu_short *)(CFG_MBAR+0x1B0012))
+#define MCFGPTB_GPTC2		(*(vu_short *)(CFG_MBAR+0x1B0014))
+#define MCFGPTB_GPTC3		(*(vu_short *)(CFG_MBAR+0x1B0016))
+#define MCFGPTB_GPTPACTL	(*(vu_char *)(CFG_MBAR+0x1B0018))
+#define MCFGPTB_GPTPAFLG	(*(vu_char *)(CFG_MBAR+0x1B0019))
+#define MCFGPTB_GPTPACNT	(*(vu_short *)(CFG_MBAR+0x1B001A))
+#define MCFGPTB_GPTPORT		(*(vu_char *)(CFG_MBAR+0x1B001D))
+#define MCFGPTB_GPTDDR		(*(vu_char *)(CFG_MBAR+0x1B001E))
+
+/* Bit level definitions and macros */
+#define MCFGPT_GPTIOS_IOS3		(0x08)
+#define MCFGPT_GPTIOS_IOS2		(0x04)
+#define MCFGPT_GPTIOS_IOS1		(0x02)
+#define MCFGPT_GPTIOS_IOS0		(0x01)
+
+#define MCFGPT_GPTCFORC_FOC3		(0x08)
+#define MCFGPT_GPTCFORC_FOC2		(0x04)
+#define MCFGPT_GPTCFORC_FOC1		(0x02)
+#define MCFGPT_GPTCFORC_FOC0		(0x01)
+
+#define MCFGPT_GPTOC3M_OC3M3		(0x08)
+#define MCFGPT_GPTOC3M_OC3M2		(0x04)
+#define MCFGPT_GPTOC3M_OC3M1		(0x02)
+#define MCFGPT_GPTOC3M_OC3M0		(0x01)
+
+#define MCFGPT_GPTOC3M_OC3D(x)		(((x)&0x04))
+
+#define MCFGPT_GPTSCR1_GPTEN		(0x80)
+#define MCFGPT_GPTSCR1_TFFCA		(0x10)
+
+#define MCFGPT_GPTTOV3			(0x08)
+#define MCFGPT_GPTTOV2			(0x04)
+#define MCFGPT_GPTTOV1			(0x02)
+#define MCFGPT_GPTTOV0			(0x01)
+
+#define MCFGPT_GPTCTL_OMOL3(x)		(((x)&0x03)<<6)
+#define MCFGPT_GPTCTL_OMOL2(x)		(((x)&0x03)<<4)
+#define MCFGPT_GPTCTL_OMOL1(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTCTL_OMOL0(x)		(((x)&0x03))
+
+#define MCFGPT_GPTCTL2_EDG3(x)		(((x)&0x03)<<6)
+#define MCFGPT_GPTCTL2_EDG2(x)		(((x)&0x03)<<4)
+#define MCFGPT_GPTCTL2_EDG1(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTCTL2_EDG0(x)		(((x)&0x03))
+
+#define MCFGPT_GPTIE_C3I		(0x08)
+#define MCFGPT_GPTIE_C2I		(0x04)
+#define MCFGPT_GPTIE_C1I		(0x02)
+#define MCFGPT_GPTIE_C0I		(0x01)
+
+#define MCFGPT_GPTSCR2_TOI 		(0x80)
+#define MCFGPT_GPTSCR2_PUPT		(0x20)
+#define MCFGPT_GPTSCR2_RDPT		(0x10)
+#define MCFGPT_GPTSCR2_TCRE		(0x08)
+#define MCFGPT_GPTSCR2_PR(x)		(((x)&0x07))
+
+#define MCFGPT_GPTFLG1_C3F		(0x08)
+#define MCFGPT_GPTFLG1_C2F		(0x04)
+#define MCFGPT_GPTFLG1_C1F		(0x02)
+#define MCFGPT_GPTFLG1_C0F		(0x01)
+
+#define MCFGPT_GPTFLG2_TOF		(0x80)
+#define MCFGPT_GPTFLG2_C3F		(0x08)
+#define MCFGPT_GPTFLG2_C2F		(0x04)
+#define MCFGPT_GPTFLG2_C1F		(0x02)
+#define MCFGPT_GPTFLG2_C0F		(0x01)
+
+#define MCFGPT_GPTPACTL_PAE		(0x40)
+#define MCFGPT_GPTPACTL_PAMOD		(0x20)
+#define MCFGPT_GPTPACTL_PEDGE		(0x10)
+#define MCFGPT_GPTPACTL_CLK_PACLK	(0x04)
+#define MCFGPT_GPTPACTL_CLK_PACLK256	(0x08)
+#define MCFGPT_GPTPACTL_CLK_PACLK65536	(0x0C)
+#define MCFGPT_GPTPACTL_CLK(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTPACTL_PAOVI		(0x02)
+#define MCFGPT_GPTPACTL_PAI		(0x01)
+
+#define MCFGPT_GPTPAFLG_PAOVF		(0x02)
+#define MCFGPT_GPTPAFLG_PAIF		(0x01)
+
+#define MCFGPT_GPTPORT_PORTT3		(0x08)
+#define MCFGPT_GPTPORT_PORTT2		(0x04)
+#define MCFGPT_GPTPORT_PORTT1		(0x02)
+#define MCFGPT_GPTPORT_PORTT0		(0x01)
+
+#define MCFGPT_GPTDDR_DDRT3		(0x08)
+#define MCFGPT_GPTDDR_DDRT2		(0x04)
+#define MCFGPT_GPTDDR_DDRT1		(0x02)
+#define MCFGPT_GPTDDR_DDRT0		(0x01)
+
+/* Coldfire Flash Module CFM */
+
+#define MCFCFM_MCR			(*(vu_short *)(CFG_MBAR+0x1D0000))
+#define MCFCFM_MCR_LOCK			(0x0400)
+#define MCFCFM_MCR_PVIE			(0x0200)
+#define MCFCFM_MCR_AEIE			(0x0100)
+#define MCFCFM_MCR_CBEIE		(0x0080)
+#define MCFCFM_MCR_CCIE			(0x0040)
+#define MCFCFM_MCR_KEYACC		(0x0020)
+
+#define MCFCFM_CLKD			(*(vu_char *)(CFG_MBAR+0x1D0002))
+
+#define MCFCFM_SEC			(*(vu_long*) (CFG_MBAR+0x1D0008))
+#define MCFCFM_SEC_KEYEN		(0x80000000)
+#define MCFCFM_SEC_SECSTAT		(0x40000000)
+
+#define MCFCFM_PROT			(*(vu_long*) (CFG_MBAR+0x1D0010))
+#define MCFCFM_SACC			(*(vu_long*) (CFG_MBAR+0x1D0014))
+#define MCFCFM_DACC			(*(vu_long*) (CFG_MBAR+0x1D0018))
+#define MCFCFM_USTAT			(*(vu_char*) (CFG_MBAR+0x1D0020))
+#define MCFCFM_USTAT_CBEIF		0x80
+#define MCFCFM_USTAT_CCIF		0x40
+#define MCFCFM_USTAT_PVIOL		0x20
+#define MCFCFM_USTAT_ACCERR		0x10
+#define MCFCFM_USTAT_BLANK		0x04
 
+#define MCFCFM_CMD			(*(vu_char*) (CFG_MBAR+0x1D0024))
+#define MCFCFM_CMD_ERSVER		0x05
+#define MCFCFM_CMD_PGERSVER		0x06
+#define MCFCFM_CMD_PGM			0x20
+#define MCFCFM_CMD_PGERS		0x40
+#define MCFCFM_CMD_MASERS		0x41
 
 /****************************************************************************/
 #endif	/* m5282_h */
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
new file mode 100644
index 000000000..f49a4b745
--- /dev/null
+++ b/include/configs/EB+MCF-EV123.h
@@ -0,0 +1,223 @@
+/*
+ * Configuation settings for the BuS EB+MCF-EV123 boards.
+ *
+ * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CONFIG_EB_MCF_EV123_H_
+#define _CONFIG_EB_MCF_EV123_H_
+
+#define  CONFIG_EB_MCF_EV123
+
+#undef DEBUG
+#undef CFG_HALT_BEFOR_RAM_JUMP
+#undef ET_DEBUG
+  
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define	CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5282			/* define processor type */
+
+#define CONFIG_MISC_INIT_R
+
+#define FEC_ENET
+#define CONFIG_ETHADDR 00:CF:52:82:EB:01
+
+#define CONFIG_BAUDRATE 9600
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
+
+#define CONFIG_BOOTCOMMAND "printenv"
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_ADDR		0xF003C000	/* End of 256K */
+#define CFG_ENV_SECT_SIZE	0x4000
+#define CFG_ENV_IS_IN_FLASH	1
+/*
+#define CFG_ENV_IS_EMBEDDED	1
+#define CFG_ENV_ADDR_REDUND		0xF0018000
+#define CFG_ENV_SECT_SIZE_REDUND	0x4000
+*/
+#else
+#define CFG_ENV_ADDR		0xFFE04000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#endif
+
+//#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
+#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5
+#define CFG_PROMPT		"\nEV123 U-Boot> "
+#define	CFG_LONGHELP				/* undef to save memory		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_LOAD_ADDR		0x20000
+
+#define CFG_MEMTEST_START	0x100000
+#define CFG_MEMTEST_END		0x400000
+/*#define CFG_DRAM_TEST		1 */
+#undef CFG_DRAM_TEST
+
+/* Clock and PLL Configuration */
+#define CFG_HZ			10000000 
+#define	CFG_CLK			58982400       /* 9,8304MHz * 6 */
+
+/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
+
+#define CFG_MFD			0x01	/* PLL Multiplication Factor Devider */	
+#define CFG_RFD			0x00	/* PLL Reduce Frecuency Devider */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define	CFG_MBAR		0x40000000
+
+#define	CFG_DISCOVER_PHY
+/* #define	CFG_ENET_BD_BASE	0x380000 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR       0x20000000
+#define CFG_INIT_RAM_END	0x10000		/* End of used area in internal SRAM	*/
+#define CFG_GBL_DATA_SIZE	64      	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE1		0x00000000
+#define	CFG_SDRAM_SIZE1		16		/* SDRAM size in MB */
+
+/*
+#define CFG_SDRAM_BASE0		CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024
+#define	CFG_SDRAM_SIZE0		16	*/	/* SDRAM size in MB */
+
+#define CFG_SDRAM_BASE		CFG_SDRAM_BASE1
+#define	CFG_SDRAM_SIZE		CFG_SDRAM_SIZE1
+
+#define CFG_FLASH_BASE		0xFFE00000
+#define	CFG_INT_FLASH_BASE	0xF0000000
+
+/* If M5282 port is fully implemented the monitor base will be behind
+ * the vector table. */
+#if (TEXT_BASE !=  CFG_INT_FLASH_BASE)
+#define CFG_MONITOR_BASE	(TEXT_BASE + 0x400) 
+#else
+#define CFG_MONITOR_BASE	(TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
+#endif
+
+#define CFG_MONITOR_LEN		0x20000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define	CFG_MAX_FLASH_SECT	35
+#define	CFG_MAX_FLASH_BANKS	2
+#define	CFG_FLASH_ERASE_TOUT	10000000
+#define	CFG_FLASH_PROTECTION
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+#define CFG_CS0_BASE		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		2*1024*1024
+#define CFG_CS0_WIDTH		16
+#define CFG_CS0_RO 		0
+#define CFG_CS0_WS		6
+
+#define CFG_CS3_BASE		0xE0000000
+#define CFG_CS3_SIZE		1*1024*1024
+#define CFG_CS3_WIDTH		16
+#define CFG_CS3_RO 		0
+#define CFG_CS3_WS		6
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_PACNT		0x0000000	/* Port A D[31:24] */
+#define CFG_PADDR		0x0000000
+#define CFG_PADAT		0x0000000
+
+#define CFG_PBCNT		0x0000000	/* Port B D[23:16] */
+#define CFG_PBDDR		0x0000000
+#define CFG_PBDAT		0x0000000
+
+#define CFG_PCCNT		0x0000000	/* Port C D[15:08] */
+#define CFG_PCDDR		0x0000000
+#define CFG_PCDAT		0x0000000
+
+#define CFG_PDCNT		0x0000000	/* Port D D[07:00] */
+#define CFG_PCDDR		0x0000000
+#define CFG_PCDAT		0x0000000
+
+#define CFG_PEHLPAR		0xC0
+#define CFG_PUAPAR		0x0F		/* UA0..UA3 = Uart 0 +1 */
+#define CFG_DDRUA		0x05
+#define CFG_PJPAR 		0xFF;
+
+/*-----------------------------------------------------------------------
+ * CCM configuration
+ */
+
+#define	CFG_CCM_SIZ		0
+
+/*---------------------------------------------------------------------*/
+#endif	/* _CONFIG_M5282EVB_H */
+/*---------------------------------------------------------------------*/
-- 
cgit v1.2.3


From 60e270a4903b3379d6859418d99aeef1d0d0cdff Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@pollux.denx.de>
Date: Thu, 20 Apr 2006 12:38:41 +0200
Subject: Fix I/O Macros and mini-app stubs for Nios-II Patch by Scott McNutt
 11, Aug 2005  -Fix asm/io.h macros  -Eliminate use of CACHE_BYPASS in cpu
 code  -Eliminate assembler warnings  -Fix mini-app stubs and force no small
 data

---
 CHANGELOG              |  7 +++++++
 cpu/nios2/epcs.c       | 23 +++++++++++++----------
 cpu/nios2/exceptions.S |  3 +++
 cpu/nios2/interrupts.c | 18 ++++++++++--------
 cpu/nios2/serial.c     | 26 ++++++++++++--------------
 cpu/nios2/sysid.c      | 11 ++++++-----
 examples/Makefile      |  2 +-
 examples/stubs.c       |  2 +-
 include/asm-nios2/io.h |  7 ++++---
 nios2_config.mk        |  2 +-
 10 files changed, 58 insertions(+), 43 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index 012fa3da7..fed7a73cb 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,13 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Fix I/O Macros and mini-app stubs for Nios-II
+  Patch by Scott McNutt 11, Aug 2005
+  -Fix asm/io.h macros
+  -Eliminate use of CACHE_BYPASS in cpu code
+  -Eliminate assembler warnings
+  -Fix mini-app stubs and force no small data
+
 * Add MCF5282 support (without preloader)
   relocate ichache_State to ram
   u-boot can run from internal flash
diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c
index a8851e99a..fd9fd8498 100644
--- a/cpu/nios2/epcs.c
+++ b/cpu/nios2/epcs.c
@@ -25,7 +25,7 @@
 
 #if defined(CFG_NIOS_EPCSBASE)
 #include <command.h>
-#include <nios2.h>
+#include <asm/io.h>
 #include <nios2-io.h>
 #include <nios2-epcs.h>
 
@@ -72,8 +72,7 @@
  */
 #define EPCS_TIMEOUT		100	/* 100 msec timeout */
 
-static nios_spi_t *epcs =
-	(nios_spi_t *)CACHE_BYPASS(CFG_NIOS_EPCSBASE);
+static nios_spi_t *epcs = (nios_spi_t *)CFG_NIOS_EPCSBASE;
 
 /***********************************************************************
  * Device access
@@ -81,16 +80,20 @@ static nios_spi_t *epcs =
 static int epcs_cs (int assert)
 {
 	ulong start;
+	unsigned tmp;
+
 
 	if (assert) {
-		epcs->control |= NIOS_SPI_SSO;
+		tmp = readl (&epcs->control);
+		writel (&epcs->control, tmp | NIOS_SPI_SSO);
 	} else {
 		/* Let all bits shift out */
 		start = get_timer (0);
-		while ((epcs->status & NIOS_SPI_TMT) == 0)
+		while ((readl (&epcs->status) & NIOS_SPI_TMT) == 0)
 			if (get_timer (start) > EPCS_TIMEOUT)
 				return (-1);
-		epcs->control &= ~NIOS_SPI_SSO;
+		tmp = readl (&epcs->control);
+		writel (&epcs->control, tmp & ~NIOS_SPI_SSO);
 	}
 	return (0);
 }
@@ -100,10 +103,10 @@ static int epcs_tx (unsigned char c)
 	ulong start;
 
 	start = get_timer (0);
-	while ((epcs->status & NIOS_SPI_TRDY) == 0)
+	while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0)
 		if (get_timer (start) > EPCS_TIMEOUT)
 			return (-1);
-	epcs->txdata = c;
+	writel (&epcs->txdata, c);
 	return (0);
 }
 
@@ -112,10 +115,10 @@ static int epcs_rx (void)
 	ulong start;
 
 	start = get_timer (0);
-	while ((epcs->status & NIOS_SPI_RRDY) == 0)
+	while ((readl (&epcs->status) & NIOS_SPI_RRDY) == 0)
 		if (get_timer (start) > EPCS_TIMEOUT)
 			return (-1);
-	return (epcs->rxdata);
+	return (readl (&epcs->rxdata));
 }
 
 static unsigned char bitrev[] = {
diff --git a/cpu/nios2/exceptions.S b/cpu/nios2/exceptions.S
index d3b95cfc7..b9c7a587e 100644
--- a/cpu/nios2/exceptions.S
+++ b/cpu/nios2/exceptions.S
@@ -30,6 +30,9 @@
 
 	.global _exception
 
+	.set noat
+	.set nobreak
+
 _exception:
 	/* SAVE ALL REGS -- this allows trap and unimplemented
 	 * instruction handlers to be coded conveniently in C
diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c
index 4a6da582b..4685161b8 100644
--- a/cpu/nios2/interrupts.c
+++ b/cpu/nios2/interrupts.c
@@ -27,6 +27,7 @@
 
 #include <nios2.h>
 #include <nios2-io.h>
+#include <asm/io.h>
 #include <asm/ptrace.h>
 #include <common.h>
 #include <command.h>
@@ -79,7 +80,7 @@ void tmr_isr (void *arg)
 	/* Interrupt is cleared by writing anything to the
 	 * status register.
 	 */
-	tmr->status = 0;
+	writel (&tmr->status, 0);
 	timestamp += CFG_NIOS_TMRMS;
 #ifdef CONFIG_STATUS_LED
 	status_led_tick(timestamp);
@@ -88,16 +89,17 @@ void tmr_isr (void *arg)
 
 static void tmr_init (void)
 {
-	nios_timer_t *tmr =(nios_timer_t *)CACHE_BYPASS(CFG_NIOS_TMRBASE);
+	nios_timer_t *tmr =(nios_timer_t *)CFG_NIOS_TMRBASE;
+
+	writel (&tmr->status, 0);
+	writel (&tmr->control, 0);
+	writel (&tmr->control, NIOS_TIMER_STOP);
 
-	tmr->control &= ~(NIOS_TIMER_START | NIOS_TIMER_ITO);
-	tmr->control |= NIOS_TIMER_STOP;
 #if defined(CFG_NIOS_TMRCNT)
-	tmr->periodl = CFG_NIOS_TMRCNT & 0xffff;
-	tmr->periodh = (CFG_NIOS_TMRCNT >> 16) & 0xffff;
+	writel (&tmr->periodl, CFG_NIOS_TMRCNT & 0xffff);
+	writel (&tmr->periodh, (CFG_NIOS_TMRCNT >> 16) & 0xffff);
 #endif
-	tmr->control |= ( NIOS_TIMER_ITO |
-			  NIOS_TIMER_CONT |
+	writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT |
 			  NIOS_TIMER_START );
 	irq_install_handler (CFG_NIOS_TMRIRQ, tmr_isr, (void *)tmr);
 }
diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c
index 3d766037a..0bd3821e3 100644
--- a/cpu/nios2/serial.c
+++ b/cpu/nios2/serial.c
@@ -24,7 +24,7 @@
 
 #include <common.h>
 #include <watchdog.h>
-#include <nios2.h>
+#include <asm/io.h>
 #include <nios2-io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -34,8 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
  *-----------------------------------------------------------------*/
 #if defined(CONFIG_CONSOLE_JTAG)
 
-static nios_jtag_t *jtag =
-	(nios_jtag_t *)CACHE_BYPASS(CFG_NIOS_CONSOLE);
+static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE;
 
 void serial_setbrg( void ){ return; }
 int serial_init( void ) { return(0);}
@@ -44,9 +43,9 @@ void serial_putc (char c)
 {
 	unsigned val;
 
-	while (NIOS_JTAG_WSPACE (jtag->control) == 0)
+	while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0)
 		WATCHDOG_RESET ();
-	jtag->data = (unsigned char)c;
+	writel (&jtag->data, (unsigned char)c);
 }
 
 void serial_puts (const char *s)
@@ -57,7 +56,7 @@ void serial_puts (const char *s)
 
 int serial_tstc (void)
 {
-	return (jtag->control & NIOS_JTAG_RRDY);
+	return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
 }
 
 int serial_getc (void)
@@ -67,7 +66,7 @@ int serial_getc (void)
 
 	while (1) {
 		WATCHDOG_RESET ();
-		val = jtag->data;
+		val = readl (&jtag->data);
 		if (val & NIOS_JTAG_RVALID)
 			break;
 	}
@@ -80,8 +79,7 @@ int serial_getc (void)
  *-----------------------------------------------------------------*/
 #else
 
-static nios_uart_t *uart = (nios_uart_t *)
-	CACHE_BYPASS(CFG_NIOS_CONSOLE);
+static nios_uart_t *uart = (nios_uart_t *) CFG_NIOS_CONSOLE;
 
 #if defined(CFG_NIOS_FIXEDBAUD)
 
@@ -98,7 +96,7 @@ void serial_setbrg (void)
 	unsigned div;
 
 	div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
-	uart->divisor = div;
+	writel (&uart->divisor,div);
 	return;
 }
 
@@ -118,9 +116,9 @@ void serial_putc (char c)
 {
 	if (c == '\n')
 		serial_putc ('\r');
-	while ((uart->status & NIOS_UART_TRDY) == 0)
+	while ((readl (&uart->status) & NIOS_UART_TRDY) == 0)
 		WATCHDOG_RESET ();
-	uart->txdata = (unsigned char)c;
+	writel (&uart->txdata,(unsigned char)c);
 }
 
 void serial_puts (const char *s)
@@ -132,14 +130,14 @@ void serial_puts (const char *s)
 
 int serial_tstc (void)
 {
-	return (uart->status & NIOS_UART_RRDY);
+	return (readl (&uart->status) & NIOS_UART_RRDY);
 }
 
 int serial_getc (void)
 {
 	while (serial_tstc () == 0)
 		WATCHDOG_RESET ();
-	return( uart->rxdata & 0x00ff );
+	return (readl (&uart->rxdata) & 0x00ff );
 }
 
 #endif /* CONFIG_JTAG_CONSOLE */
diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c
index 2b7a569cc..b5a29593e 100644
--- a/cpu/nios2/sysid.c
+++ b/cpu/nios2/sysid.c
@@ -26,20 +26,21 @@
 #if defined (CFG_NIOS_SYSID_BASE)
 
 #include <command.h>
-#include <nios2.h>
+#include <asm/io.h>
 #include <nios2-io.h>
 #include <linux/time.h>
 
 void display_sysid (void)
 {
-	struct nios_sysid_t *sysid =
-		(struct nios_sysid_t *)CACHE_BYPASS(CFG_NIOS_SYSID_BASE);
+	struct nios_sysid_t *sysid = (struct nios_sysid_t *)CFG_NIOS_SYSID_BASE;
 	struct tm t;
 	char asc[32];
+	time_t stamp;
 
-	localtime_r ((time_t *)&sysid->timestamp, &t);
+	stamp = readl (&sysid->timestamp);
+	localtime_r (&stamp, &t);
 	asctime_r (&t, asc);
-	printf ("SYSID : %08x, %s", sysid->id, asc);
+	printf ("SYSID : %08x, %s", readl (&sysid->id), asc);
 
 }
 
diff --git a/examples/Makefile b/examples/Makefile
index fee26741d..a342d7506 100644
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -42,7 +42,7 @@ LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds
 endif
 
 ifeq ($(ARCH),nios2)
-LOAD_ADDR = 0x00800000 -L $(gcclibdir) -T nios2.lds
+LOAD_ADDR = 0x02000000 -L $(gcclibdir) -T nios2.lds
 endif
 
 ifeq ($(ARCH),m68k)
diff --git a/examples/stubs.c b/examples/stubs.c
index 250a9af6e..1caa57574 100644
--- a/examples/stubs.c
+++ b/examples/stubs.c
@@ -92,7 +92,7 @@ gd_t *global_data;
 #x ":\n"				\
 "	movhi	r8, %%hi(%0)\n"		\
 "	ori	r8, r0, %%lo(%0)\n"	\
-"	add	r8, r0, r15\n"		\
+"	add	r8, r8, r15\n"		\
 "	ldw	r8, 0(r8)\n"		\
 "	ldw	r8, %1(r8)\n"		\
 "	jmp	r8\n"			\
diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h
index b16a98865..0fab53bf0 100644
--- a/include/asm-nios2/io.h
+++ b/include/asm-nios2/io.h
@@ -39,12 +39,13 @@ extern unsigned inl (unsigned port);
 #define readl(addr)\
 	({unsigned long val;\
 	 asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
+
 #define writeb(addr,val)\
-	asm volatile ("stbio %0, 0(%1)" : : "r" (addr), "r" (val))
+	asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val))
 #define writew(addr,val)\
-	asm volatile ("sthio %0, 0(%1)" : : "r" (addr), "r" (val))
+	asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val))
 #define writel(addr,val)\
-	asm volatile ("stwio %0, 0(%1)" : : "r" (addr), "r" (val))
+	asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val))
 
 #define inb(addr)	readb(addr)
 #define inw(addr)	readw(addr)
diff --git a/nios2_config.mk b/nios2_config.mk
index 03253a364..3f23b56c9 100644
--- a/nios2_config.mk
+++ b/nios2_config.mk
@@ -23,4 +23,4 @@
 #
 
 PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__
-PLATFORM_CPPFLAGS += -ffixed-r15
+PLATFORM_CPPFLAGS += -ffixed-r15 -G0
-- 
cgit v1.2.3


From 7fd392c2d0b27e372a1771e0bda877820b30d6e0 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@pollux.denx.de>
Date: Thu, 20 Apr 2006 12:49:05 +0200
Subject: * Add EPCS Controller bootrom work-around for Nios-II   Patch from
 Scott McNutt 11, Aug 2005    -When booting from an epcs controller, the epcs
 bootrom may leave the     slave select in an asserted state causing soft
 reset hang. This     patch ensures slave select is negated at reset.

---
 CHANGELOG            |  8 +++++++-
 cpu/nios2/epcs.c     | 15 +++++++++++++++
 include/nios2-epcs.h |  5 +++++
 lib_nios2/board.c    | 10 ++++++++++
 4 files changed, 37 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index fed7a73cb..9014e73f1 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,8 +2,14 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Add EPCS Controller bootrom work-around for Nios-II
+   Patch from Scott McNutt 11, Aug 2005
+   -When booting from an epcs controller, the epcs bootrom may leave the
+    slave select in an asserted state causing soft reset hang. This
+    patch ensures slave select is negated at reset.
+
 * Fix I/O Macros and mini-app stubs for Nios-II
-  Patch by Scott McNutt 11, Aug 2005
+  Patch from Scott McNutt 11, Aug 2005
   -Fix asm/io.h macros
   -Eliminate use of CACHE_BYPASS in cpu code
   -Eliminate assembler warnings
diff --git a/cpu/nios2/epcs.c b/cpu/nios2/epcs.c
index fd9fd8498..414c38c2b 100644
--- a/cpu/nios2/epcs.c
+++ b/cpu/nios2/epcs.c
@@ -210,6 +210,21 @@ static struct epcs_devinfo_t devinfo[] = {
 	{ 0, 0, 0, 0, 0, 0 }
 };
 
+int epcs_reset (void)
+{
+	/* When booting from an epcs controller, the epcs bootrom
+	 * code may leave the slave select in an asserted state.
+	 * This causes two problems: (1) The initial epcs access
+	 * will fail -- not a big deal, and (2) a software reset
+	 * will cause the bootrom code to hang since it does not
+	 * ensure the select is negated prior to first access -- a
+	 * big deal. Here we just negate chip select and everything
+	 * gets better :-)
+	 */
+	epcs_cs (0); /* Negate chip select */
+	return (0);
+}
+
 epcs_devinfo_t *epcs_dev_find (void)
 {
 	unsigned char buf[4];
diff --git a/include/nios2-epcs.h b/include/nios2-epcs.h
index 2c9522cfd..20e0c87c8 100644
--- a/include/nios2-epcs.h
+++ b/include/nios2-epcs.h
@@ -38,6 +38,11 @@ typedef struct epcs_devinfo_t {
 	unsigned char   prot_mask;	/* Protection mask */
 }epcs_devinfo_t;
 
+/* Resets the epcs controller -- to prevent (potential) soft-reset
+ * problems when booting from the epcs controller
+ */
+extern int epcs_reset (void);
+
 /* Returns the devinfo struct if EPCS device is found;
  * NULL otherwise.
  */
diff --git a/lib_nios2/board.c b/lib_nios2/board.c
index cd2303777..7ffb3f019 100644
--- a/lib_nios2/board.c
+++ b/lib_nios2/board.c
@@ -31,6 +31,9 @@
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
 #endif
+#if defined(CFG_NIOS_EPCSBASE)
+#include <nios2-epcs.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -93,6 +96,9 @@ init_fnc_t *init_sequence[] = {
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 	board_early_init_f,	/* Call board-specific init code early.*/
 #endif
+#if defined(CFG_NIOS_EPCSBASE)
+	epcs_reset,
+#endif
 
 	env_init,
 	serial_init,
@@ -165,6 +171,10 @@ void board_init (void)
 	WATCHDOG_RESET ();
 	interrupt_init ();
 
+#if defined(CONFIG_BOARD_LATE_INIT)
+	board_late_init ();
+#endif
+
 	/* main_loop */
 	for (;;) {
 		WATCHDOG_RESET ();
-- 
cgit v1.2.3


From a83531bb628535afba9a298eddadd247a8383e29 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@pollux.denx.de>
Date: Thu, 20 Apr 2006 12:57:43 +0200
Subject: * Update PK1C20 board for Nios-II 5.0   Patch from Scott McNutt, 11
 Aug 2005   -Update base addresses for standard configuration   -Eliminate use
 of CACHE_BYPASS in board code

---
 CHANGELOG                       |  9 +++++--
 board/psyent/common/AMDLV065D.c | 57 ++++++++++++++++++-----------------------
 board/psyent/pk1c20/config.mk   |  2 +-
 board/psyent/pk1c20/led.c       | 14 +++++-----
 include/configs/PK1C20.h        | 20 +++++++--------
 5 files changed, 50 insertions(+), 52 deletions(-)

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index 9014e73f1..c8b16a663 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,14 +2,19 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Update PK1C20 board for Nios-II 5.0 
+  Patch from Scott McNutt, 11 Aug 2005
+  -Update base addresses for standard configuration
+  -Eliminate use of CACHE_BYPASS in board code
+
 * Add EPCS Controller bootrom work-around for Nios-II
-   Patch from Scott McNutt 11, Aug 2005
+   Patch from Scott McNutt, 11 Aug 2005
    -When booting from an epcs controller, the epcs bootrom may leave the
     slave select in an asserted state causing soft reset hang. This
     patch ensures slave select is negated at reset.
 
 * Fix I/O Macros and mini-app stubs for Nios-II
-  Patch from Scott McNutt 11, Aug 2005
+  Patch from Scott McNutt, 11 Aug 2005
   -Fix asm/io.h macros
   -Eliminate use of CACHE_BYPASS in cpu code
   -Eliminate assembler warnings
diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c
index 4965743bd..8a7b14ee2 100644
--- a/board/psyent/common/AMDLV065D.c
+++ b/board/psyent/common/AMDLV065D.c
@@ -26,7 +26,7 @@
 #if defined(CONFIG_NIOS)
 #include <nios.h>
 #else
-#include <nios2.h>
+#include <asm/io.h>
 #endif
 
 #define SECTSZ		(64 * 1024)
@@ -56,9 +56,8 @@ unsigned long flash_init (void)
 void flash_print_info (flash_info_t * info)
 {
 	int i, k;
-	unsigned long size;
 	int erased;
-	volatile unsigned char *flash;
+	unsigned long *addr;
 
 	printf ("  Size: %ld KB in %d Sectors\n",
 		info->size >> 10, info->sector_count);
@@ -66,14 +65,10 @@ void flash_print_info (flash_info_t * info)
 	for (i = 0; i < info->sector_count; ++i) {
 
 		/* Check if whole sector is erased */
-		if (i != (info->sector_count - 1))
-			size = info->start[i + 1] - info->start[i];
-		else
-			size = info->start[0] + info->size - info->start[i];
 		erased = 1;
-		flash = (volatile unsigned char *) CACHE_BYPASS(info->start[i]);
-		for (k = 0; k < size; k++) {
-			if (*flash++ != 0xff) {
+		addr = (unsigned long *) info->start[i];
+		for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
+			if ( readl(addr++) != (unsigned long)-1) {
 				erased = 0;
 				break;
 			}
@@ -83,7 +78,7 @@ void flash_print_info (flash_info_t * info)
 		if ((i % 5) == 0)
 			printf ("\n   ");
 		printf (" %08lX%s%s",
-			CACHE_NO_BYPASS(info->start[i]),
+			info->start[i],
 			erased ? " E" : "  ",
 			info->protect[i] ? "RO " : "   ");
 	}
@@ -95,9 +90,8 @@ void flash_print_info (flash_info_t * info)
 
 int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)
-		CACHE_BYPASS(info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	unsigned char *addr = (unsigned char *) info->start[0];
+	unsigned char *addr2;
 	int prot, sect;
 	ulong start;
 
@@ -127,19 +121,18 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	 */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *)
-				CACHE_BYPASS((info->start[sect]));
-			*addr = 0xaa;
-			*addr = 0x55;
-			*addr = 0x80;
-			*addr = 0xaa;
-			*addr = 0x55;
-			*addr2 = 0x30;
+			addr2 = (unsigned char *) info->start[sect];
+			writeb (addr, 0xaa);
+			writeb (addr,  0x55);
+			writeb (addr,  0x80);
+			writeb (addr,  0xaa);
+			writeb (addr,  0x55);
+			writeb (addr2, 0x30);
 			/* Now just wait for 0xff & provide some user
 			 * feedback while we wait.
 			 */
 			start = get_timer (0);
-			while (*addr2 != 0xff) {
+			while ( readb (addr2) != 0xff) {
 				udelay (1000 * 1000);
 				putc ('.');
 				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
@@ -163,27 +156,27 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 
-	vu_char *cmd = (vu_char *) CACHE_BYPASS(info->start[0]);
-	vu_char *dst = (vu_char *) CACHE_BYPASS(addr);
+	vu_char *cmd = (vu_char *) info->start[0];
+	vu_char *dst = (vu_char *) addr;
 	unsigned char b;
 	ulong start;
 
 	while (cnt) {
 		/* Check for sufficient erase */
 		b = *src;
-		if ((*dst & b) != b) {
-			printf ("%02x : %02x\n", *dst, b);
+		if ((readb (dst) & b) != b) {
+			printf ("%02x : %02x\n", readb (dst), b);
 			return (2);
 		}
 
-		*cmd = 0xaa;
-		*cmd = 0x55;
-		*cmd = 0xa0;
-		*dst = b;
+		writeb (cmd,  0xaa);
+		writeb (cmd,  0x55);
+		writeb (cmd,  0xa0);
+		writeb (dst, b);
 
 		/* Verify write */
 		start = get_timer (0);
-		while (*dst != b) {
+		while (readb (dst) != b) {
 			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
 				return 1;
 			}
diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk
index d72bceed2..d65780dd9 100644
--- a/board/psyent/pk1c20/config.mk
+++ b/board/psyent/pk1c20/config.mk
@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-TEXT_BASE = 0x018e0000
+TEXT_BASE = 0x01fc0000
 
 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
 PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c
index c175c9b87..c75fe8c57 100644
--- a/board/psyent/pk1c20/led.c
+++ b/board/psyent/pk1c20/led.c
@@ -22,7 +22,7 @@
  */
 
 #include <common.h>
-#include <nios2.h>
+#include <asm/io.h>
 #include <nios2-io.h>
 #include <status_led.h>
 
@@ -33,30 +33,30 @@ static led_id_t val = 0;
 
 void __led_init (led_id_t mask, int state)
 {
-	nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
 
 	if (state == STATUS_LED_ON)
 		val &= ~mask;
 	else
 		val |= mask;
-	pio->data = val;
+	writel (&pio->data, val);
 }
 
 void __led_set (led_id_t mask, int state)
 {
-	nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
 
 	if (state == STATUS_LED_ON)
 		val &= ~mask;
 	else
 		val |= mask;
-	pio->data = val;
+	writel (&pio->data, val);
 }
 
 void __led_toggle (led_id_t mask)
 {
-	nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
 
 	val ^= mask;
-	pio->data = val;
+	writel (&pio->data, val);
 }
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index 91e95186a..83a7ec27b 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -32,7 +32,7 @@
 
 #define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
 #define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
-#define CFG_NIOS_SYSID_BASE	0x00920828	/* System id address	*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
 
 /*------------------------------------------------------------------------
@@ -51,7 +51,7 @@
 #define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
 #define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
 #define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
-#define CFG_SRAM_BASE		0x00800000	/* SRAM base addr	*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
 #define CFG_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
 
 /*------------------------------------------------------------------------
@@ -61,7 +61,7 @@
  *	-Global data is placed below the heap.
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128k		*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
 #define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
 #define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
 
@@ -95,9 +95,9 @@
  * CONSOLE
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CONSOLE_JTAG)
-#define CFG_NIOS_CONSOLE	0x00920820	/* JTAG UART base addr	*/
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
 #else
-#define CFG_NIOS_CONSOLE	0x009208a0	/* UART base addr	*/
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
 #endif
 
 #define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
@@ -110,9 +110,9 @@
  * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
  * epcs device access is enabled. The base address is the epcs
  * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
- * The register base is currently at offset 0x400 from the memory base.
+ * The register base is currently at offset 0x600 from the memory base.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_EPCSBASE	0x00900400	/* EPCS register base	*/
+#define CFG_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
 
 /*------------------------------------------------------------------------
  * DEBUG
@@ -126,7 +126,7 @@
  * registers, we can slow it down to 10 msec using TMRCNT. If the default
  * period is acceptable, TMRCNT can be left undefined.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_TMRBASE	0x00920860	/* Tick timer base addr */
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
 #define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
 #define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
 #define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
@@ -137,7 +137,7 @@
  * must implement its own led routines -- leds are, after all,
  * board-specific, no?
  *----------------------------------------------------------------------*/
-#define CFG_LEDPIO_ADDR		0x00920840	/* LED PIO base addr	*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
 #define CONFIG_STATUS_LED			/* Enable status driver */
 
 #define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
@@ -150,7 +150,7 @@
  * way out to avoid changes there -- define the base address to ensure
  * cache bypass so there's no need to monkey with inx/outx macros.
  *----------------------------------------------------------------------*/
-#define CONFIG_SMC91111_BASE	0x80910300	/* Base addr (bypass)	*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
 #define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
 #undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
 #define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
-- 
cgit v1.2.3


From 0e0ef590b263927a62d399dce0cf1b7aa8dee42e Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@pollux.denx.de>
Date: Wed, 26 Apr 2006 08:13:18 +0200
Subject: Add Altera Nios-II boards EP1C20, EP1S10 and EP1S40 Patch from Scott
 McNutt, 11 Aug 2005

---
 CHANGELOG                       |   3 +
 MAINTAINERS                     |   3 +
 MAKEALL                         |   2 +-
 Makefile                        |   9 ++
 README                          |   1 +
 board/altera/common/AMDLV065D.c | 190 ++++++++++++++++++++++++++++++++++++++
 board/altera/common/epled.c     |  62 +++++++++++++
 board/altera/ep1c20/Makefile    |  50 ++++++++++
 board/altera/ep1c20/config.mk   |  31 +++++++
 board/altera/ep1c20/ep1c20.c    |  40 ++++++++
 board/altera/ep1c20/u-boot.lds  | 136 +++++++++++++++++++++++++++
 board/altera/ep1s10/Makefile    |  50 ++++++++++
 board/altera/ep1s10/config.mk   |  31 +++++++
 board/altera/ep1s10/ep1s10.c    |  40 ++++++++
 board/altera/ep1s10/u-boot.lds  | 136 +++++++++++++++++++++++++++
 board/altera/ep1s40/Makefile    |  50 ++++++++++
 board/altera/ep1s40/config.mk   |  31 +++++++
 board/altera/ep1s40/ep1s40.c    |  35 +++++++
 board/altera/ep1s40/u-boot.lds  | 136 +++++++++++++++++++++++++++
 include/configs/EP1C20.h        | 199 ++++++++++++++++++++++++++++++++++++++++
 include/configs/EP1S10.h        | 193 ++++++++++++++++++++++++++++++++++++++
 include/configs/EP1S40.h        | 193 ++++++++++++++++++++++++++++++++++++++
 22 files changed, 1620 insertions(+), 1 deletion(-)
 create mode 100644 board/altera/common/AMDLV065D.c
 create mode 100644 board/altera/common/epled.c
 create mode 100644 board/altera/ep1c20/Makefile
 create mode 100644 board/altera/ep1c20/config.mk
 create mode 100644 board/altera/ep1c20/ep1c20.c
 create mode 100644 board/altera/ep1c20/u-boot.lds
 create mode 100644 board/altera/ep1s10/Makefile
 create mode 100644 board/altera/ep1s10/config.mk
 create mode 100644 board/altera/ep1s10/ep1s10.c
 create mode 100644 board/altera/ep1s10/u-boot.lds
 create mode 100644 board/altera/ep1s40/Makefile
 create mode 100644 board/altera/ep1s40/config.mk
 create mode 100644 board/altera/ep1s40/ep1s40.c
 create mode 100644 board/altera/ep1s40/u-boot.lds
 create mode 100644 include/configs/EP1C20.h
 create mode 100644 include/configs/EP1S10.h
 create mode 100644 include/configs/EP1S40.h

(limited to 'include')

diff --git a/CHANGELOG b/CHANGELOG
index c8b16a663..aac832dcc 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Add Altera Nios-II boards EP1C20, EP1S10 and EP1S40
+  Patch from Scott McNutt, 11 Aug 2005
+
 * Update PK1C20 board for Nios-II 5.0 
   Patch from Scott McNutt, 11 Aug 2005
   -Update base addresses for standard configuration
diff --git a/MAINTAINERS b/MAINTAINERS
index 0ef9e0349..a6c0efa23 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -511,6 +511,9 @@ Scott McNutt <smcnutt@psyent.com>
 
 	PCI5441			Nios-II
 	PK1C20			Nios-II
+	EP1C20			Nios-II
+	EP1S10			Nios-II
+	EP1S40			Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#
diff --git a/MAKEALL b/MAKEALL
index d3bd0325d..75ec51336 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -265,7 +265,7 @@ LIST_nios="	\
 ## Nios-II Systems
 #########################################################################
 
-LIST_nios2="PCI5441 PK1C20"
+LIST_nios2="PCI5441 PK1C20 EP1C20 EP1S10 EP1S40"
 
 #########################################################################
 ## MicroBlaze Systems
diff --git a/Makefile b/Makefile
index 7fd82e974..86640a6bb 100644
--- a/Makefile
+++ b/Makefile
@@ -1885,6 +1885,15 @@ ADNPESC1_config: unconfig
 ## Nios-II
 #########################################################################
 
+EP1C20_config : unconfig
+	@./mkconfig  EP1C20 nios2 nios2 ep1c20 altera
+
+EP1S10_config : unconfig
+	@./mkconfig  EP1S10 nios2 nios2 ep1s10 altera
+
+EP1S40_config : unconfig
+	@./mkconfig  EP1S40 nios2 nios2 ep1s40 altera
+
 PK1C20_config : unconfig
 	@./mkconfig  PK1C20 nios2 nios2 pk1c20 psyent
 
diff --git a/README b/README
index 3ae9cfcc1..2369dd085 100644
--- a/README
+++ b/README
@@ -322,6 +322,7 @@ The following options need to be configured:
 		------------------------
 
 		CONFIG_PCI5441 CONFIG_PK1C20
+		CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40
 
 
 - CPU Module Type: (if CONFIG_COGENT is defined)
diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c
new file mode 100644
index 000000000..8a7b14ee2
--- /dev/null
+++ b/board/altera/common/AMDLV065D.c
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#if defined(CONFIG_NIOS)
+#include <nios.h>
+#else
+#include <asm/io.h>
+#endif
+
+#define SECTSZ		(64 * 1024)
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*----------------------------------------------------------------------*/
+unsigned long flash_init (void)
+{
+	int i;
+	unsigned long addr;
+	flash_info_t *fli = &flash_info[0];
+
+	fli->size = CFG_FLASH_SIZE;
+	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
+
+	addr = CFG_FLASH_BASE;
+	for (i = 0; i < fli->sector_count; ++i) {
+		fli->start[i] = addr;
+		addr += SECTSZ;
+		fli->protect[i] = 1;
+	}
+
+	return (CFG_FLASH_SIZE);
+}
+/*--------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+	int i, k;
+	int erased;
+	unsigned long *addr;
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+
+		/* Check if whole sector is erased */
+		erased = 1;
+		addr = (unsigned long *) info->start[i];
+		for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
+			if ( readl(addr++) != (unsigned long)-1) {
+				erased = 0;
+				break;
+			}
+		}
+
+		/* Print the info */
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-------------------------------------------------------------------*/
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	unsigned char *addr = (unsigned char *) info->start[0];
+	unsigned char *addr2;
+	int prot, sect;
+	ulong start;
+
+	/* Some sanity checking */
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* It's ok to erase multiple sectors provided we don't delay more
+	 * than 50 usec between cmds ... at which point the erase time-out
+	 * occurs. So don't go and put printf() calls in the loop ... it
+	 * won't be very helpful ;-)
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (unsigned char *) info->start[sect];
+			writeb (addr, 0xaa);
+			writeb (addr,  0x55);
+			writeb (addr,  0x80);
+			writeb (addr,  0xaa);
+			writeb (addr,  0x55);
+			writeb (addr2, 0x30);
+			/* Now just wait for 0xff & provide some user
+			 * feedback while we wait.
+			 */
+			start = get_timer (0);
+			while ( readb (addr2) != 0xff) {
+				udelay (1000 * 1000);
+				putc ('.');
+				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
+			}
+		}
+	}
+	printf ("\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+
+	vu_char *cmd = (vu_char *) info->start[0];
+	vu_char *dst = (vu_char *) addr;
+	unsigned char b;
+	ulong start;
+
+	while (cnt) {
+		/* Check for sufficient erase */
+		b = *src;
+		if ((readb (dst) & b) != b) {
+			printf ("%02x : %02x\n", readb (dst), b);
+			return (2);
+		}
+
+		writeb (cmd,  0xaa);
+		writeb (cmd,  0x55);
+		writeb (cmd,  0xa0);
+		writeb (dst, b);
+
+		/* Verify write */
+		start = get_timer (0);
+		while (readb (dst) != b) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return 1;
+			}
+		}
+		dst++;
+		src++;
+		cnt--;
+	}
+
+	return (0);
+}
diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c
new file mode 100644
index 000000000..c75fe8c57
--- /dev/null
+++ b/board/altera/common/epled.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <nios2-io.h>
+#include <status_led.h>
+
+/* The LED port is configured as output only, so we
+ * must track the state manually.
+ */
+static led_id_t val = 0;
+
+void __led_init (led_id_t mask, int state)
+{
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+
+	if (state == STATUS_LED_ON)
+		val &= ~mask;
+	else
+		val |= mask;
+	writel (&pio->data, val);
+}
+
+void __led_set (led_id_t mask, int state)
+{
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+
+	if (state == STATUS_LED_ON)
+		val &= ~mask;
+	else
+		val |= mask;
+	writel (&pio->data, val);
+}
+
+void __led_toggle (led_id_t mask)
+{
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+
+	val ^= mask;
+	writel (&pio->data, val);
+}
diff --git a/board/altera/ep1c20/Makefile b/board/altera/ep1c20/Makefile
new file mode 100644
index 000000000..a92b25833
--- /dev/null
+++ b/board/altera/ep1c20/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+COMOBJS := ../common/AMDLV065D.o ../common/epled.o
+
+OBJS	:= $(BOARD).o $(COMOBJS)
+
+SOBJS	=
+
+$(LIB): $(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/altera/ep1c20/config.mk b/board/altera/ep1c20/config.mk
new file mode 100644
index 000000000..dab274083
--- /dev/null
+++ b/board/altera/ep1c20/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01fc0000
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/altera/ep1c20/ep1c20.c b/board/altera/ep1c20/ep1c20.c
new file mode 100644
index 000000000..29491391e
--- /dev/null
+++ b/board/altera/ep1c20/ep1c20.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("BOARD : Altera EP-1C20\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}
diff --git a/board/altera/ep1c20/u-boot.lds b/board/altera/ep1c20/u-boot.lds
new file mode 100644
index 000000000..b99b82c82
--- /dev/null
+++ b/board/altera/ep1c20/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios2/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(.rodata)
+	  *(.rodata.*)
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}
diff --git a/board/altera/ep1s10/Makefile b/board/altera/ep1s10/Makefile
new file mode 100644
index 000000000..a92b25833
--- /dev/null
+++ b/board/altera/ep1s10/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+COMOBJS := ../common/AMDLV065D.o ../common/epled.o
+
+OBJS	:= $(BOARD).o $(COMOBJS)
+
+SOBJS	=
+
+$(LIB): $(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/altera/ep1s10/config.mk b/board/altera/ep1s10/config.mk
new file mode 100644
index 000000000..dab274083
--- /dev/null
+++ b/board/altera/ep1s10/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01fc0000
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/altera/ep1s10/ep1s10.c b/board/altera/ep1s10/ep1s10.c
new file mode 100644
index 000000000..9c7e28e68
--- /dev/null
+++ b/board/altera/ep1s10/ep1s10.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("BOARD : Altera EP-1S10\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}
diff --git a/board/altera/ep1s10/u-boot.lds b/board/altera/ep1s10/u-boot.lds
new file mode 100644
index 000000000..b99b82c82
--- /dev/null
+++ b/board/altera/ep1s10/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios2/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(.rodata)
+	  *(.rodata.*)
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}
diff --git a/board/altera/ep1s40/Makefile b/board/altera/ep1s40/Makefile
new file mode 100644
index 000000000..a92b25833
--- /dev/null
+++ b/board/altera/ep1s40/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+COMOBJS := ../common/AMDLV065D.o ../common/epled.o
+
+OBJS	:= $(BOARD).o $(COMOBJS)
+
+SOBJS	=
+
+$(LIB): $(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/altera/ep1s40/config.mk b/board/altera/ep1s40/config.mk
new file mode 100644
index 000000000..dab274083
--- /dev/null
+++ b/board/altera/ep1s40/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01fc0000
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/altera/ep1s40/ep1s40.c b/board/altera/ep1s40/ep1s40.c
new file mode 100644
index 000000000..cb7555047
--- /dev/null
+++ b/board/altera/ep1s40/ep1s40.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int checkboard (void)
+{
+	puts ("BOARD : Altera EP-1S40\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}
diff --git a/board/altera/ep1s40/u-boot.lds b/board/altera/ep1s40/u-boot.lds
new file mode 100644
index 000000000..b99b82c82
--- /dev/null
+++ b/board/altera/ep1s40/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios2/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(.rodata)
+	  *(.rodata.*)
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}
diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h
new file mode 100644
index 000000000..5507f352b
--- /dev/null
+++ b/include/configs/EP1C20.h
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define CONFIG_EP1C20		1		/* EP1C20 board		*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CFG_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
+ * CFG_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CFG_ENV_ADDR	(CFG_RESET_ADDR + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#else
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#endif
+
+#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
+ * epcs device access is enabled. The base address is the epcs
+ * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
+ * The register base is currently at offset 0x600 from the memory base.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, we can slow it down to 10 msec using TMRCNT. If the default
+ * period is acceptable, TMRCNT can be left undefined.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+
+/*------------------------------------------------------------------------
+ * STATUS LED -- Provides a simple blinking led. For Nios2 each board
+ * must implement its own led routines -- leds are, after all,
+ * board-specific, no?
+ *----------------------------------------------------------------------*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_STATUS_LED			/* Enable status driver */
+
+#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+
+/*------------------------------------------------------------------------
+ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
+ * and really doesn't need any additional clutter. So I choose the lazy
+ * way out to avoid changes there -- define the base address to ensure
+ * cache bypass so there's no need to monkey with inx/outx macros.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
+#define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_ECHO	| \
+				 CFG_CMD_ENV	| \
+				 CFG_CMD_FLASH	| \
+				 CFG_CMD_IMI	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_LOADS	| \
+				 CFG_CMD_LOADB	| \
+				 CFG_CMD_MEMORY | \
+				 CFG_CMD_MISC	| \
+				 CFG_CMD_NET	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_RUN	| \
+				 CFG_CMD_SAVES	)
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP				/* Provide extended help*/
+#define CFG_PROMPT		"==> "		/* Command prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O buf size */
+#define CFG_MAXARGS		16		/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
+#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h
new file mode 100644
index 000000000..6eca9f23d
--- /dev/null
+++ b/include/configs/EP1S10.h
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define CONFIG_EP1S10		1		/* EP1S10 board		*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CFG_SRAM_SIZE		0x00100000	/* 1 MB			*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 256*1024) /* 256k heap */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
+ * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom
+ * of flash memory. This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#else
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#endif
+
+#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * EPCS Device -- None for stratix.
+ *----------------------------------------------------------------------*/
+#undef CFG_NIOS_EPCSBASE
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, we can slow it down to 10 msec using TMRCNT. If the default
+ * period is acceptable, TMRCNT can be left undefined.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+
+/*------------------------------------------------------------------------
+ * STATUS LED -- Provides a simple blinking led. For Nios2 each board
+ * must implement its own led routines -- since leds are board-specific.
+ *----------------------------------------------------------------------*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_STATUS_LED			/* Enable status driver */
+
+#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+
+/*------------------------------------------------------------------------
+ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
+ * and really doesn't need any additional clutter. So I choose the lazy
+ * way out to avoid changes there -- define the base address to ensure
+ * cache bypass so there's no need to monkey with inx/outx macros.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
+#define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_ECHO	| \
+				 CFG_CMD_ENV	| \
+				 CFG_CMD_FLASH	| \
+				 CFG_CMD_IMI	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_LOADS	| \
+				 CFG_CMD_LOADB	| \
+				 CFG_CMD_MEMORY | \
+				 CFG_CMD_MISC	| \
+				 CFG_CMD_NET	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_RUN	| \
+				 CFG_CMD_SAVES	)
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP				/* Provide extended help*/
+#define CFG_PROMPT		"==> "		/* Command prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O buf size */
+#define CFG_MAXARGS		16		/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
+#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h
new file mode 100644
index 000000000..976e79acb
--- /dev/null
+++ b/include/configs/EP1S40.h
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define CONFIG_EP1S40		1		/* EP1S40 board		*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CFG_SRAM_SIZE		0x00100000	/* 1 MB			*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 256*1024) /* 256k heap */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
+ * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom
+ * of flash memory. This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#else
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#endif
+
+#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * EPCS Device -- None for stratix.
+ *----------------------------------------------------------------------*/
+#undef CFG_NIOS_EPCSBASE
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, we can slow it down to 10 msec using TMRCNT. If the default
+ * period is acceptable, TMRCNT can be left undefined.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+
+/*------------------------------------------------------------------------
+ * STATUS LED -- Provides a simple blinking led. For Nios2 each board
+ * must implement its own led routines -- since leds are board-specific.
+ *----------------------------------------------------------------------*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_STATUS_LED			/* Enable status driver */
+
+#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+
+/*------------------------------------------------------------------------
+ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
+ * and really doesn't need any additional clutter. So I choose the lazy
+ * way out to avoid changes there -- define the base address to ensure
+ * cache bypass so there's no need to monkey with inx/outx macros.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
+#define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_ECHO	| \
+				 CFG_CMD_ENV	| \
+				 CFG_CMD_FLASH	| \
+				 CFG_CMD_IMI	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_LOADS	| \
+				 CFG_CMD_LOADB	| \
+				 CFG_CMD_MEMORY | \
+				 CFG_CMD_MISC	| \
+				 CFG_CMD_NET	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_RUN	| \
+				 CFG_CMD_SAVES	)
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP				/* Provide extended help*/
+#define CFG_PROMPT		"==> "		/* Command prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O buf size */
+#define CFG_MAXARGS		16		/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
+#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_H */
-- 
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