From a2bb7105a79af8f2ffa9f87256fce6c1cbcbd8e1 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 24 Feb 2009 10:44:02 +0100 Subject: ARM: add an "eet" variant of the imx31_phycore board The "eet" variant of the imx31_phycore board has an OLED display, using a s6e63d6 display controller on the first SPI interface, using GPIO57 as a chip-select for it. With this configuration you can display 256 colour BMP images in 16-bit RGB (RGB565) LCD mode. Signed-off-by: Guennadi Liakhovetski Acked-by: Jean-Christophe PLAGNIOL-VILLARD --- include/asm-arm/arch-mx31/mx31-regs.h | 16 ++++++++++++++++ include/configs/imx31_phycore.h | 23 +++++++++++++++++++++++ 2 files changed, 39 insertions(+) (limited to 'include') diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index 3cdaa0247..a8a05c873 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -134,7 +134,14 @@ #define MUX_CTL_CSPI2_SS0 0x85 #define MUX_CTL_CSPI2_SS1 0x86 #define MUX_CTL_CSPI2_SS2 0x87 +#define MUX_CTL_CSPI1_SS2 0x88 +#define MUX_CTL_CSPI1_SCLK 0x89 +#define MUX_CTL_CSPI1_SPI_RDY 0x8a #define MUX_CTL_CSPI2_MOSI 0x8b +#define MUX_CTL_CSPI1_MOSI 0x8c +#define MUX_CTL_CSPI1_MISO 0x8d +#define MUX_CTL_CSPI1_SS0 0x8e +#define MUX_CTL_CSPI1_SS1 0x8f /* * Helper macros for the MUX_[contact name]__[pin function] macros @@ -160,6 +167,15 @@ IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC) #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC) +#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC) +#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC) +#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC) +#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC) +#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC) +#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \ + IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC) +#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC) + #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1) diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index f0d28ee05..2dd9e92f8 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -178,4 +178,27 @@ #undef CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_DEV "nor0" +/* EET platform additions */ +#ifdef CONFIG_IMX31_PHYCORE_EET +#define BOARD_LATE_INIT + +#define CONFIG_MX31_GPIO 1 + +#define CONFIG_HARD_SPI 1 +#define CONFIG_MXC_SPI 1 +#define CONFIG_CMD_SPI + +#define CONFIG_S6E63D6 1 + +#define CONFIG_LCD 1 +#define CONFIG_VIDEO_MX3 1 +#define CONFIG_SYS_WHITE_ON_BLACK 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_SPLASH_SCREEN 1 +#define CONFIG_CMD_BMP 1 +#endif + #endif /* __CONFIG_H */ -- cgit v1.2.3