From eb3f0f68ba384f179bb57ad8d5b0cd095eb4d7a4 Mon Sep 17 00:00:00 2001 From: Michael Brandt Date: Thu, 22 Oct 2009 09:51:29 +0200 Subject: new files for u8500 support. --- include/asm-arm/arch-stw8500/bits.h | 59 ++++ include/asm-arm/arch-stw8500/common.h | 134 +++++++++ include/asm-arm/arch-stw8500/emmc.h | 37 +++ include/asm-arm/arch-stw8500/gpio.h | 524 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-stw8500/mmc.h | 85 ++++++ include/asm-arm/arch-stw8500/mtu.h | 66 +++++ include/configs/u8500.h | 226 +++++++++++++++ 7 files changed, 1131 insertions(+) create mode 100755 include/asm-arm/arch-stw8500/bits.h create mode 100755 include/asm-arm/arch-stw8500/common.h create mode 100755 include/asm-arm/arch-stw8500/emmc.h create mode 100755 include/asm-arm/arch-stw8500/gpio.h create mode 100755 include/asm-arm/arch-stw8500/mmc.h create mode 100755 include/asm-arm/arch-stw8500/mtu.h create mode 100755 include/configs/u8500.h (limited to 'include') diff --git a/include/asm-arm/arch-stw8500/bits.h b/include/asm-arm/arch-stw8500/bits.h new file mode 100755 index 000000000..08e16a2a8 --- /dev/null +++ b/include/asm-arm/arch-stw8500/bits.h @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2009 + * STEricsson, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif diff --git a/include/asm-arm/arch-stw8500/common.h b/include/asm-arm/arch-stw8500/common.h new file mode 100755 index 000000000..b6185081a --- /dev/null +++ b/include/asm-arm/arch-stw8500/common.h @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2009 + * STEricsson, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _COMMON_H_ +#define _COMMON_H_ +#include + +#define PASS (1) +#define FAIL (0) + +#define IO(addr) (*((u32*) (addr))) +#define HIO(addr) (*((u16*) (addr))) +#define BIO(addr) (*((u8*) (addr))) + +/* + * macro to get at IO space + */ +#define IO_ADDRESS(x) (x) + +#define REG_WRITE_BITS(reg,val,mask,sb) (writel(((readl(reg) & ~(mask)) | (((val)<<(sb)) & (mask))), reg)) + +#define nmdk_error(format, arg...) printf(": " format "\n" , ## arg) + +#if !defined(FALSE) && !defined(TRUE) +typedef enum {FALSE, TRUE} t_bool; +#else /* FALSE & TRUE already defined */ +typedef enum {BOOL_FALSE, BOOL_TRUE} t_bool; +#endif /* !defined(FALSE) && !defined(TRUE) */ + +/*----------------------------------------------------------------------------- + * Bit mask definition + *---------------------------------------------------------------------------*/ +#define MASK_NULL8 0x00 +#define MASK_NULL16 0x0000 +#define MASK_NULL32 0x00000000 +#define MASK_ALL8 0xFF +#define MASK_ALL16 0xFFFF +#define MASK_ALL32 0xFFFFFFFF + +#define MASK_BIT0 (1UL<<0) +#define MASK_BIT1 (1UL<<1) +#define MASK_BIT2 (1UL<<2) +#define MASK_BIT3 (1UL<<3) +#define MASK_BIT4 (1UL<<4) +#define MASK_BIT5 (1UL<<5) +#define MASK_BIT6 (1UL<<6) +#define MASK_BIT7 (1UL<<7) +#define MASK_BIT8 (1UL<<8) +#define MASK_BIT9 (1UL<<9) +#define MASK_BIT10 (1UL<<10) +#define MASK_BIT11 (1UL<<11) +#define MASK_BIT12 (1UL<<12) +#define MASK_BIT13 (1UL<<13) +#define MASK_BIT14 (1UL<<14) +#define MASK_BIT15 (1UL<<15) +#define MASK_BIT16 (1UL<<16) +#define MASK_BIT17 (1UL<<17) +#define MASK_BIT18 (1UL<<18) +#define MASK_BIT19 (1UL<<19) +#define MASK_BIT20 (1UL<<20) +#define MASK_BIT21 (1UL<<21) +#define MASK_BIT22 (1UL<<22) +#define MASK_BIT23 (1UL<<23) +#define MASK_BIT24 (1UL<<24) +#define MASK_BIT25 (1UL<<25) +#define MASK_BIT26 (1UL<<26) +#define MASK_BIT27 (1UL<<27) +#define MASK_BIT28 (1UL<<28) +#define MASK_BIT29 (1UL<<29) +#define MASK_BIT30 (1UL<<30) +#define MASK_BIT31 (1UL<<31) + +#define NOMADIK_INTERNAL_ERROR (-8) +#define NOMADIK_NOT_CONFIGURED (-7) +#define NOMADIK_REQUEST_PENDING (-6) +#define NOMADIK_REQUEST_NOT_APPLICABLE (-5) +#define NOMADIK_INVALID_PARAMETER (-4) +#define NOMADIK_UNSUPPORTED_FEATURE (-3) +#define NOMADIK_UNSUPPORTED_HW (-2) +#define NOMADIK_ERROR (-1) +#define NOMADIK_OK ( 0) +#define NOMADIK_INTERNAL_EVENT ( 1) +#define NOMADIK_REMAINING_PENDING_EVENTS ( 2) +#define NOMADIK_REMAINING_FILTER_PENDING_EVENTS ( 3) +#define NOMADIK_NO_MORE_PENDING_EVENT ( 4) +#define NOMADIK_NO_MORE_FILTER_PENDING_EVENT ( 5) +#define NOMADIK_NO_PENDING_EVENT_ERROR ( 7) + + +#define NOMADIK_MAX_ERROR_VALUE (-65) /* HW specific error codes + * should start from this offset + */ +/*----------------------------------------------------------------------------- + * Bit setting or clearing + *---------------------------------------------------------------------------*/ +#define NOMADIK_SET_BITS(reg,mask) ((reg) |= (mask)) +#define NOMADIK_CLEAR_BITS(reg,mask) ((reg) &= ~(mask)) +#define NOMADIK_READ_BITS(reg,mask) ((reg) & (mask)) +#define NOMADIK_WRITE_BITS(reg,val,mask) ((reg) = (((reg) & ~(mask)) | ((val) & (mask)))) +#define NOMADIK_READ_REG(reg) (reg) +#define NOMADIK_WRITE_REG(reg,val) ((reg) = (val)) + +/* + * Definition of the different kind of addresses manipulated into a system with MMU + * (handle physical AND logical addresses) + */ + +typedef u32 t_physical_address; +typedef u32 t_logical_address; + +/*function prototypes*/ +void gpio_init(void); +int emmc_init (u8); + +#endif /* _COMMON_H_ */ diff --git a/include/asm-arm/arch-stw8500/emmc.h b/include/asm-arm/arch-stw8500/emmc.h new file mode 100755 index 000000000..aa4b48df0 --- /dev/null +++ b/include/asm-arm/arch-stw8500/emmc.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2009 + * STEricsson, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _STM_EMMC_H +#define _STM_EMMC_H + + +#include + +extern int emmc_init (u8); +int emmc_erase(u32, u32); +int emmc_read (u32,u32,u32); +int emmc_write(u32,u32,u32); +int emmc_write_pib(void); + + +#endif /* !defined(_STM_EMMC_H) */ diff --git a/include/asm-arm/arch-stw8500/gpio.h b/include/asm-arm/arch-stw8500/gpio.h new file mode 100755 index 000000000..26e14d04c --- /dev/null +++ b/include/asm-arm/arch-stw8500/gpio.h @@ -0,0 +1,524 @@ +/* + * (C) Copyright 2009 + * STEricsson, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MOP500_GPIO_h +#define _MOP500_GPIO_h + +#include +#include +#include + +#include "common.h" +#include + +#define GPIO_TOTAL_PINS 268 + +#define GPIO_PINS_PER_BLOCK 32 +#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK +1) +#define GPIO_BLOCK(pin) ( ( ( pin + GPIO_PINS_PER_BLOCK ) >> 5) - 1 ) + + +struct gpio_register { + u32 gpio_dat; /* GPIO data register *//*0x000 */ + u32 gpio_dats; /* GPIO data Set register *//*0x004 */ + u32 gpio_datc; /* GPIO data Clear register *//*0x008 */ + u32 gpio_pdis; /* GPIO Pull disable register *//*0x00C */ + u32 gpio_dir; /* GPIO data direction register *//*0x010 */ + u32 gpio_dirs; /* GPIO data dir Set register *//*0x014 */ + u32 gpio_dirc; /* GPIO data dir Clear register *//*0x018 */ + u32 gpio_slpm; /* GPIO Sleep mode register *//*0x01C */ + u32 gpio_afsa; /* GPIO AltFun A Select reg *//*0x020 */ + u32 gpio_afsb; /* GPIO AltFun B Select reg *//*0x024 */ + u32 gpio_lowemi; /* GPIO low EMI Select reg *//*0x028 */ + u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/ + u32 gpio_rimsc; /* GPIO rising edge intr set/clear *//*0x040 */ + u32 gpio_fimsc; /* GPIO falling edge interrupt set/clear register *//*0x044 */ + u32 gpio_mis; /* GPIO masked interrupt status register *//*0x048 */ + u32 gpio_ic; /* GPIO Interrupt Clear register *//*0x04C */ + u32 gpio_rwimsc; /* GPIO Rising-edge Wakeup IMSC register *//*0x050 */ + u32 gpio_fwimsc; /* GPIO Falling-edge Wakeup IMSC register *//*0x054 */ + u32 gpio_wks; /* GPIO Wakeup Status register *//*0x058 */ +}; + +/* Error values returned by functions */ +typedef enum { + GPIO_OK = 0, /* (0) */ + GPIO_UNSUPPORTED_HW = -2, /* NOMADIK_UNSUPPORTED_HW, (-2) */ + GPIO_UNSUPPORTED_FEATURE = -3, /* NOMADIK_UNSUPPORTED_FEATURE, (-3) */ + GPIO_INVALID_PARAMETER = -4, /* NOMADIK_INVALID_PARAMETER, (-4) */ + GPIO_REQUEST_NOT_APPLICABLE = -5, /* NOMADIK_REQUEST_NOT_APPLICABLE, (-5) */ + GPIO_REQUEST_PENDING = -6, /* NOMADIK_REQUEST_PENDING, (-6) */ + GPIO_NOT_CONFIGURED = -7, /* NOMADIK_NOT_CONFIGURED, (-7) */ + GPIO_INTERNAL_ERROR = -8, /* NOMADIK_INTERNAL_ERROR, (-8) */ + GPIO_INTERNAL_EVENT = 1, /* NOMADIK_INTERNAL_EVENT,*/ + GPIO_REMAINING_EVENT = 2, /* NOMADIK_REMAINING_PENDING_EVENTS,*/ + GPIO_NO_MORE_PENDING_EVENT = 3, /* NOMADIK_NO_MORE_PENDING_EVENT,*/ + GPIO_INVALID_CLIENT = -25, + GPIO_INVALID_PIN = -26, + GPIO_PIN_BUSY = -27, + GPIO_PIN_NOT_ALLOCATED = -28, + GPIO_WRONG_CLIENT = -29, + GPIO_UNSUPPORTED_ALTFUNC = -30, + +} gpio_error; + +/*GPIO DEVICE ID */ +typedef enum { + GPIO_DEVICE_ID_0, + GPIO_DEVICE_ID_1, + GPIO_DEVICE_ID_2, + GPIO_DEVICE_ID_3, + GPIO_DEVICE_ID_INVALID +} gpio_device_id; + +/* + * Pin description To be used in SOFTWARE mode: refers to a pin. + */ +typedef enum { + GPIO_PIN_0, + GPIO_PIN_1, + GPIO_PIN_2, + GPIO_PIN_3, + GPIO_PIN_4, + GPIO_PIN_5, + GPIO_PIN_6, + GPIO_PIN_7, + GPIO_PIN_8, + GPIO_PIN_9, + GPIO_PIN_10, + GPIO_PIN_11, + GPIO_PIN_12, + GPIO_PIN_13, + GPIO_PIN_14, + GPIO_PIN_15, + GPIO_PIN_16, + GPIO_PIN_17, + GPIO_PIN_18, + GPIO_PIN_19, + GPIO_PIN_20, + GPIO_PIN_21, + GPIO_PIN_22, + GPIO_PIN_23, + GPIO_PIN_24, + GPIO_PIN_25, + GPIO_PIN_26, + GPIO_PIN_27, + GPIO_PIN_28, + GPIO_PIN_29, + GPIO_PIN_30, + GPIO_PIN_31, + GPIO_PIN_32, + GPIO_PIN_33, + GPIO_PIN_34, + GPIO_PIN_35, + GPIO_PIN_36, + GPIO_PIN_37, + GPIO_PIN_38, + GPIO_PIN_39, + GPIO_PIN_40, + GPIO_PIN_41, + GPIO_PIN_42, + GPIO_PIN_43, + GPIO_PIN_44, + GPIO_PIN_45, + GPIO_PIN_46, + GPIO_PIN_47, + GPIO_PIN_48, + GPIO_PIN_49, + GPIO_PIN_50, + GPIO_PIN_51, + GPIO_PIN_52, + GPIO_PIN_53, + GPIO_PIN_54, + GPIO_PIN_55, + GPIO_PIN_56, + GPIO_PIN_57, + GPIO_PIN_58, + GPIO_PIN_59, + GPIO_PIN_60, + GPIO_PIN_61, + GPIO_PIN_62, + GPIO_PIN_63, + GPIO_PIN_64, + GPIO_PIN_65, + GPIO_PIN_66, + GPIO_PIN_67, + GPIO_PIN_68, + GPIO_PIN_69, + GPIO_PIN_70, + GPIO_PIN_71, + GPIO_PIN_72, + GPIO_PIN_73, + GPIO_PIN_74, + GPIO_PIN_75, + GPIO_PIN_76, + GPIO_PIN_77, + GPIO_PIN_78, + GPIO_PIN_79, + GPIO_PIN_80, + GPIO_PIN_81, + GPIO_PIN_82, + GPIO_PIN_83, + GPIO_PIN_84, + GPIO_PIN_85, + GPIO_PIN_86, + GPIO_PIN_87, + GPIO_PIN_88, + GPIO_PIN_89, + GPIO_PIN_90, + GPIO_PIN_91, + GPIO_PIN_92, + GPIO_PIN_93, + GPIO_PIN_94, + GPIO_PIN_95, + GPIO_PIN_96, + GPIO_PIN_97, + GPIO_PIN_98, + GPIO_PIN_99, + GPIO_PIN_100, + GPIO_PIN_101, + GPIO_PIN_102, + GPIO_PIN_103, + GPIO_PIN_104, + GPIO_PIN_105, + GPIO_PIN_106, + GPIO_PIN_107, + GPIO_PIN_108, + GPIO_PIN_109, + GPIO_PIN_110, + GPIO_PIN_111, + GPIO_PIN_112, + GPIO_PIN_113, + GPIO_PIN_114, + GPIO_PIN_115, + GPIO_PIN_116, + GPIO_PIN_117, + GPIO_PIN_118, + GPIO_PIN_119, + GPIO_PIN_120, + GPIO_PIN_121, + GPIO_PIN_122, + GPIO_PIN_123, + GPIO_PIN_124, + GPIO_PIN_125, + GPIO_PIN_126, + GPIO_PIN_127, + GPIO_PIN_128, + GPIO_PIN_129, + GPIO_PIN_130, + GPIO_PIN_131, + GPIO_PIN_132, + GPIO_PIN_133, + GPIO_PIN_134, + GPIO_PIN_135, + GPIO_PIN_136, + GPIO_PIN_137, + GPIO_PIN_138, + GPIO_PIN_139, + GPIO_PIN_140, + GPIO_PIN_141, + GPIO_PIN_142, + GPIO_PIN_143, + GPIO_PIN_144, + GPIO_PIN_145, + GPIO_PIN_146, + GPIO_PIN_147, + GPIO_PIN_148, + GPIO_PIN_149, + GPIO_PIN_150, + GPIO_PIN_151, + GPIO_PIN_152, + GPIO_PIN_153, + GPIO_PIN_154, + GPIO_PIN_155, + GPIO_PIN_156, + GPIO_PIN_157, + GPIO_PIN_158, + GPIO_PIN_159, + GPIO_PIN_160, + GPIO_PIN_161, + GPIO_PIN_162, + GPIO_PIN_163, + GPIO_PIN_164, + GPIO_PIN_165, + GPIO_PIN_166, + GPIO_PIN_167, + GPIO_PIN_168, + GPIO_PIN_169, + GPIO_PIN_170, + GPIO_PIN_171, + GPIO_PIN_172, + GPIO_PIN_173, + GPIO_PIN_174, + GPIO_PIN_175, + GPIO_PIN_176, + GPIO_PIN_177, + GPIO_PIN_178, + GPIO_PIN_179, + GPIO_PIN_180, + GPIO_PIN_181, + GPIO_PIN_182, + GPIO_PIN_183, + GPIO_PIN_184, + GPIO_PIN_185, + GPIO_PIN_186, + GPIO_PIN_187, + GPIO_PIN_188, + GPIO_PIN_189, + GPIO_PIN_190, + GPIO_PIN_191, + GPIO_PIN_192, + GPIO_PIN_193, + GPIO_PIN_194, + GPIO_PIN_195, + GPIO_PIN_196, + GPIO_PIN_197, + GPIO_PIN_198, + GPIO_PIN_199, + GPIO_PIN_200, + GPIO_PIN_201, + GPIO_PIN_202, + GPIO_PIN_203, + GPIO_PIN_204, + GPIO_PIN_205, + GPIO_PIN_206, + GPIO_PIN_207, + GPIO_PIN_208, + GPIO_PIN_209, + GPIO_PIN_210, + GPIO_PIN_211, + GPIO_PIN_212, + GPIO_PIN_213, + GPIO_PIN_214, + GPIO_PIN_215, + GPIO_PIN_216, + GPIO_PIN_217, + GPIO_PIN_218, + GPIO_PIN_219, + GPIO_PIN_220, + GPIO_PIN_221, + GPIO_PIN_222, + GPIO_PIN_223, + GPIO_PIN_224, + GPIO_PIN_225, + GPIO_PIN_226, + GPIO_PIN_227, + GPIO_PIN_228, + GPIO_PIN_229, + GPIO_PIN_230, + GPIO_PIN_231, + GPIO_PIN_232, + GPIO_PIN_233, + GPIO_PIN_234, + GPIO_PIN_235, + GPIO_PIN_236, + GPIO_PIN_237, + GPIO_PIN_238, + GPIO_PIN_239, + GPIO_PIN_240, + GPIO_PIN_241, + GPIO_PIN_242, + GPIO_PIN_243, + GPIO_PIN_244, + GPIO_PIN_245, + GPIO_PIN_246, + GPIO_PIN_247, + GPIO_PIN_248, + GPIO_PIN_249, + GPIO_PIN_250, + GPIO_PIN_251, + GPIO_PIN_252, + GPIO_PIN_253, + GPIO_PIN_254, + GPIO_PIN_255, + GPIO_PIN_256, + GPIO_PIN_257, + GPIO_PIN_258, + GPIO_PIN_259, + GPIO_PIN_260, + GPIO_PIN_261, + GPIO_PIN_262, + GPIO_PIN_263, + GPIO_PIN_264, + GPIO_PIN_265, + GPIO_PIN_266, + GPIO_PIN_267 +} gpio_pin; + +/* + * Alternate Function: + * refered in altfun_table to pointout particular altfun to be enabled + * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation + */ +typedef enum { + GPIO_ALT_UART_0_MODEM, + GPIO_ALT_UART_0_NO_MODEM, + GPIO_ALT_UART_1, + GPIO_ALT_UART_2, + GPIO_ALT_I2C_0, + GPIO_ALT_I2C_1, + GPIO_ALT_MSP_0, + GPIO_ALT_MSP_1, + GPIO_ALT_MSP_2, + GPIO_ALT_MSP_3, + GPIO_ALT_MSP_4, + GPIO_ALT_MSP_5, + GPIO_ALT_SSP_0, + GPIO_ALT_SSP_1, + GPIO_ALT_MM_CARD0, + GPIO_ALT_SD_CARD0, + GPIO_ALT_DMA_0, + GPIO_ALT_DMA_1, + GPIO_ALT_HSI0, + GPIO_ALT_CCIR656_INPUT, + GPIO_ALT_CCIR656_OUTPUT, + GPIO_ALT_LCD_PANEL, + GPIO_ALT_MDIF, + GPIO_ALT_SDRAM, + GPIO_ALT_HAMAC_AUDIO_DBG, + GPIO_ALT_HAMAC_VIDEO_DBG, + GPIO_ALT_CLOCK_RESET, + GPIO_ALT_TSP, + GPIO_ALT_IRDA, + GPIO_ALT_USB_MINIMUM, + GPIO_ALT_USB_I2C, + GPIO_ALT_OWM, + GPIO_ALT_PWL, + GPIO_ALT_FSMC, + GPIO_ALT_COMP_FLASH, + GPIO_ALT_SRAM_NOR_FLASH, + GPIO_ALT_FSMC_ADDLINE_0_TO_15, + GPIO_ALT_SCROLL_KEY, + GPIO_ALT_MSHC, + GPIO_ALT_HPI, + GPIO_ALT_USB_OTG, + GPIO_ALT_SDIO, + GPIO_ALT_HSMMC, + GPIO_ALT_FSMC_ADD_DATA_0_TO_25, + GPIO_ALT_HSI1, + GPIO_ALT_NOR, + GPIO_ALT_NAND, + GPIO_ALT_KEYPAD, + GPIO_ALT_VPIP, + GPIO_ALT_CAM, + GPIO_ALT_CCP1, + GPIO_ALT_EMMC, +#ifdef CONFIG_NOMADIK_8500_V1 + GPIO_ALT_POP_EMMC, +#endif + GPIO_ALT_FUNMAX /* Add new alt func before this */ +} gpio_alt_function; + +/* Defines pin assignment(Software mode or Alternate mode) */ +typedef enum { + GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ + GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */ + GPIO_ALTF_A, /* Pin connected to alternate function 1 (HW periph 1) */ + GPIO_ALTF_B, /* Pin connected to alternate function 2 (HW periph 2) */ + GPIO_ALTF_C, /* Pin connected to alternate function 3 (HW periph 3) */ + GPIO_ALTF_FIND, /* Pin connected to alternate function 3 (HW periph 3) */ + GPIO_ALTF_DISABLE /* Pin connected to alternate function 3 (HW periph 3) */ +} gpio_mode; + +/* Defines GPIO pin direction */ +typedef enum { + GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ + GPIO_DIR_INPUT, /* GPIO set as input */ + GPIO_DIR_OUTPUT /* GPIO set as output */ +} gpio_direction; + +/* Interrupt trigger mode */ +typedef enum { + GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored by the function */ + GPIO_TRIG_DISABLE, /* Triggers no IT */ + GPIO_TRIG_RISING_EDGE, /* Triggers an IT on a rising edge */ + GPIO_TRIG_FALLING_EDGE, /* Triggers an IT on a falling edge */ + GPIO_TRIG_BOTH_EDGES, /* Triggers an IT on a rising and a falling edge */ + GPIO_TRIG_HIGH_LEVEL, /* Triggers an IT on a high level */ + GPIO_TRIG_LOW_LEVEL /* Triggers an IT on a low level */ +} gpio_trig; /* Interrupt trigger mode, or disable */ + +/* Configuration parameters for one GPIO pin.*/ +typedef struct { + gpio_mode mode; /* Defines mode (SOFTWARE or Alternate). */ + gpio_direction direction; /* Define pin direction (in SOFTWARE mode only). */ + gpio_trig trig; /* Interrupt trigger (in SOFTWARE mode only) */ + char *dev_name; /* Name of client driver who owns the gpio pin */ +} gpio_config; + +/* GPIO pin data*/ +typedef enum { + GPIO_DATA_LOW, /* GPIO pin status is low. */ + GPIO_DATA_HIGH /* GPIO pin status is high. */ +} gpio_data; + +/* GPIO behaviour in sleep mode */ +typedef enum { + GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ + GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull up/down enabled + when in sleep mode. */ + GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by GPIO IP. So mode, + direction and data values for GPIO pin in + sleep mode are determined by configuration + set to GPIO pin before entering to sleep mode. */ +} gpio_sleep_mode; + +/* GPIO ability to wake the system up from sleep mode.*/ +typedef enum { + GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ + GPIO_WAKE_DISABLE, /* GPIO will not wake the system from sleep mode. */ + GPIO_WAKE_LOW_LEVEL, /* GPIO will wake the system up on a LOW level. */ + GPIO_WAKE_HIGH_LEVEL, /* GPIO will wake the system up on a HIGH level. */ + GPIO_WAKE_RISING_EDGE, /* GPIO will wake the system up on a RISING edge. */ + GPIO_WAKE_FALLING_EDGE, /* GPIO will wake the system up on a FALLING edge. */ + GPIO_WAKE_BOTH_EDGES /* GPIO will wake the system up on both RISING and FALLING edge. */ +} gpio_wake; + +/* Configuration parameters for one GPIO pin in sleep mode.*/ +typedef struct { + gpio_sleep_mode sleep_mode; /* GPIO behaviour in sleep mode. */ + gpio_wake wake; /* GPIO ability to wake up the system. */ +} gpio_sleep_config; + +/*------------------------------------------------------------------------ + * Functions declaration + * refer ./Documentation/arm/STM-Nomadik/gpio_user_guide.txt + *----------------------------------------------------------------------*/ + +extern int gpio_setpinconfig(gpio_pin pin_id, gpio_config * pin_config); +extern int gpio_resetpinconfig(gpio_pin pin_id, char *dev_name); +extern int gpio_writepin(gpio_pin pin_id, gpio_data value, char *dev_name); +extern int gpio_readpin(gpio_pin pin_id, gpio_data * value); +extern int gpio_altfuncenable(gpio_alt_function altfunc, + char *dev_name); +extern int gpio_altfuncdisable(gpio_alt_function altfunc, + char *dev_name); + +struct gpio_altfun_data { + u16 altfun; + u16 start; + u16 end; + t_bool cont; + u8 type; +}; + +#endif /* __INC_GPIO_H */ diff --git a/include/asm-arm/arch-stw8500/mmc.h b/include/asm-arm/arch-stw8500/mmc.h new file mode 100755 index 000000000..c8aa4d71c --- /dev/null +++ b/include/asm-arm/arch-stw8500/mmc.h @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2009 + * STEricsson, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __MMC_NOMADIK_P_H__ +#define __MMC_NOMADIK_P_H__ + +#define MAX_ERROR_VALUE -65 +typedef enum +{ + /* MMC specific error defines */ + MMC_CMD_CRC_FAIL = (MAX_ERROR_VALUE - 1), /* Command response received (but CRC check failed) */ + MMC_DATA_CRC_FAIL = (MAX_ERROR_VALUE - 2), /* Data bock sent/received (CRC check Failed) */ + MMC_CMD_RSP_TIMEOUT = (MAX_ERROR_VALUE - 3), /* Command response timeout */ + MMC_DATA_TIMEOUT = (MAX_ERROR_VALUE - 4), /* Data time out*/ + MMC_TX_UNDERRUN = (MAX_ERROR_VALUE - 5), /* Transmit FIFO under-run */ + MMC_RX_OVERRUN = (MAX_ERROR_VALUE - 6), /* Receive FIFO over-run */ + MMC_START_BIT_ERR = (MAX_ERROR_VALUE - 7), /* Start bit not detected on all data signals in widE bus mode */ + MMC_CMD_OUT_OF_RANGE = (MAX_ERROR_VALUE - 8), /* CMD's argument was out of range.*/ + MMC_ADDR_MISALIGNED = (MAX_ERROR_VALUE - 9), /* Misaligned address */ + MMC_BLOCK_LEN_ERR = (MAX_ERROR_VALUE - 10), /* Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ + MMC_ERASE_SEQ_ERR = (MAX_ERROR_VALUE - 11), /* An error in the sequence of erase command occurs.*/ + MMC_BAD_ERASE_PARAM = (MAX_ERROR_VALUE - 12), /* An Invalid selection for erase groups */ + MMC_WRITE_PROT_VIOLATION = (MAX_ERROR_VALUE - 13), /* Attempt to program a write protect block */ + MMC_LOCK_UNLOCK_FAILED = (MAX_ERROR_VALUE - 14), /* Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ + MMC_COM_CRC_FAILED = (MAX_ERROR_VALUE - 15), /* CRC check of the previous command failed */ + MMC_ILLEGAL_CMD = (MAX_ERROR_VALUE - 16), /* Command is not legal for the card state */ + MMC_CARD_ECC_FAILED = (MAX_ERROR_VALUE - 17), /* Card internal ECC was applied but failed to correct the data */ + MMC_CC_ERROR = (MAX_ERROR_VALUE - 18), /* Internal card controller error */ + MMC_GENERAL_UNKNOWN_ERROR = (MAX_ERROR_VALUE - 19), /* General or Unknown error */ + MMC_STREAM_READ_UNDERRUN = (MAX_ERROR_VALUE - 20), /* The card could not sustain data transfer in stream read operation. */ + MMC_STREAM_WRITE_OVERRUN = (MAX_ERROR_VALUE - 21), /* The card could not sustain data programming in stream mode */ + MMC_CID_CSD_OVERWRITE = (MAX_ERROR_VALUE - 22), /* CID/CSD overwrite error */ + MMC_WP_ERASE_SKIP = (MAX_ERROR_VALUE - 23), /* only partial address space was erased */ + MMC_CARD_ECC_DISABLED = (MAX_ERROR_VALUE - 24), /* Command has been executed without using internal ECC */ + MMC_ERASE_RESET = (MAX_ERROR_VALUE - 25), /* Erase sequence was cleared before executing because an out of erase sequence command was received */ + MMC_AKE_SEQ_ERROR = (MAX_ERROR_VALUE - 26), /* Error in sequence of authentication. */ + MMC_INVALID_VOLTRANGE = (MAX_ERROR_VALUE - 27), + MMC_ADDR_OUT_OF_RANGE = (MAX_ERROR_VALUE - 28), + MMC_SWITCH_ERROR = (MAX_ERROR_VALUE - 29), + MMC_SDIO_DISABLED = (MAX_ERROR_VALUE - 30), + MMC_SDIO_FUNCTION_BUSY = (MAX_ERROR_VALUE - 31), + MMC_SDIO_FUNCTION_FAILED = (MAX_ERROR_VALUE - 32), + MMC_SDIO_UNKNOWN_FUNCTION = MAX_ERROR_VALUE, + + /* standard error defines */ + MMC_INTERNAL_ERROR = -8, + MMC_NOT_CONFIGURED = -7, + MMC_REQUEST_PENDING = -6, + MMC_REQUEST_NOT_APPLICABLE = -5, + MMC_INVALID_PARAMETER = -4, + MMC_UNSUPPORTED_FEATURE = -3, + MMC_UNSUPPORTED_HW = -2, + MMC_ERROR = -1, + MMC_OK = 0, + MMC_INTERNAL_EVENT = 1, + MMC_REMAINING_PENDING_EVENTS = 2, + MMC_REMAINING_FILTER_PENDING_EVENTS = 3, + MMC_NO_MORE_PENDING_EVENT = 4, + MMC_NO_MORE_FILTER_PENDING_EVENT = 5, + MMC_NO_PENDING_EVENT_ERROR = 7, +} t_mmc_error; + +int init_mmc_card(void); + +#endif + diff --git a/include/asm-arm/arch-stw8500/mtu.h b/include/asm-arm/arch-stw8500/mtu.h new file mode 100755 index 000000000..a87be9ef4 --- /dev/null +++ b/include/asm-arm/arch-stw8500/mtu.h @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2009 Alessandro Rubini + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MTU_H +#define __ASM_ARCH_MTU_H + +/* + * The MTU device hosts four different counters, with 4 set of + * registers. These are register names. + */ + +#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ +#define MTU_RIS 0x04 /* Raw interrupt status */ +#define MTU_MIS 0x08 /* Masked interrupt status */ +#define MTU_ICR 0x0C /* Interrupt clear register */ + +/* per-timer registers take 0..3 as argument */ +#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ +#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ +#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ +#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ + +/* bits for the control register */ +#define MTU_CRn_ENA 0x80 +#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ +#define MTU_CRn_PRESCALE_MASK 0x0c +#define MTU_CRn_PRESCALE_1 0x00 +#define MTU_CRn_PRESCALE_16 0x04 +#define MTU_CRn_PRESCALE_256 0x08 +#define MTU_CRn_32BITS 0x02 +#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ + +/* Other registers are usual amba/primecell registers, currently not used */ +#define MTU_ITCR 0xff0 +#define MTU_ITOP 0xff4 + +#define MTU_PERIPH_ID0 0xfe0 +#define MTU_PERIPH_ID1 0xfe4 +#define MTU_PERIPH_ID2 0xfe8 +#define MTU_PERIPH_ID3 0xfeC + +#define MTU_PCELL0 0xff0 +#define MTU_PCELL1 0xff4 +#define MTU_PCELL2 0xff8 +#define MTU_PCELL3 0xffC + +#endif /* __ASM_ARCH_MTU_H */ diff --git a/include/configs/u8500.h b/include/configs/u8500.h new file mode 100755 index 000000000..331258d18 --- /dev/null +++ b/include/configs/u8500.h @@ -0,0 +1,226 @@ +/* + * (C) Copyright 2009 + * STEricsson, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_U8500 1 +#define CONFIG_U8500_ED 1 +#define CONFIG_L2_OFF 1 + +#define PCI_IO_VADDR 0xee000000 + +#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) + +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF +#define CONFIG_SYS_HZ 1000//(2400000 / 128) /* Timer0 is clocked at 2.4Mhz with 256 divider */ + +#ifndef CONFIG_U8500_V1 +#define CONFIG_SYS_TIMERBASE 0xA03DA000 /* MTU0 timer */ +#else +#define CONFIG_SYS_TIMERBASE 0xA03C6000 /* MTU0 timer */ +#endif + +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ + +#define BOARD_LATE_INIT 1 +#define LITTLEENDIAN + +/*----------------------------------------------------------------------- + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE 128*1024 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/*----------------------------------------------------------------------- + * PL011 Configuration + */ + +#define CONFIG_PL011_SERIAL +/* + * U8500 UART registers base for 3 serial devices + */ +#define CFG_UART0_BASE 0x80120000 +#define CFG_UART1_BASE 0x80121000 +#define CFG_UART2_BASE 0x80007000 +#define CFG_SERIAL0 CFG_UART0_BASE +#define CFG_SERIAL1 CFG_UART1_BASE +#define CFG_SERIAL2 CFG_UART2_BASE +#define CONFIG_PL011_CLOCK 38400000 +#define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1), (void *) (CFG_SERIAL2) } +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +// do_fat_read will loop (insane timeout), e.g. fail, if this is defined +#define CONFIG_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_BDI +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MISC +#define CONFIG_CMD_RUN +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EMMC + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTARGS "cachepolicy=writealloc root=/dev/ram0 initrd=0x800000,20M init=linuxrc rw console=ttyAMA2,115200n8 mem=256M board_id=0" +#define CONFIG_BOOTCOMMAND "emmc_read 0x100000 0x280000 0x200000; bootm 0x100000" + +#ifndef CONFIG_USB_TTY +#define CONFIG_PREBOOT "mmc init;mmc_read_cmd_file" +#endif +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "U8500 $ " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_LOAD_ADDR 0x800000 /* default load address */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING + + +#define CONFIG_SETUP_MEMORY_TAGS 2 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ + +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* we have dual bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ +#define PHYS_SDRAM_SIZE_1 0x10000000 /* 256 MB */ +#define PHYS_SDRAM_2 0x20000000 /* DDR-SDRAM Bank #2 */ +#define PHYS_SDRAM_SIZE_2 0x10000000 /* 256 MB */ + +/*----------------------------------------------------------------------- + * MMC related configs + */ +#define MMC_BLOCK_SIZE 512 +#define CFG_MMC_BASE 0x80126000 /* MMC base for 8500 */ + +/*----------------------------------------------------------------------- + * EMMC related configs + */ +#define CFG_EMMC_BASE 0x80114000 /* EMMC base of size 2GB for 8500 */ +#define CONFIG_CMD_ENV +#define CONFIG_ENV_IS_IN_EMMC 1 +#define CONFIG_ENV_OFFSET_START 0x260000 +#define CONFIG_ENV_OFFSET_END 0x27F000 + +/*----------------------------------------------------------------------- + * USB related configs + */ +#define CONFIG_USB_BASE 0xA03E0000 + +#ifdef CONFIG_USB_TTY +#define CONFIG_ARM +#define CONFIG_USBTTY "cdc_acm" +#define CONFIG_USB_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define __LITTLE_ENDIAN 1 +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE +#endif +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#ifndef CONFIG_U8500_V1 + +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ + +#else + +#define CFG_POP_EMMC_BASE 0x80005000 /*POP EMMC base of size 256MB for 8500 cut1.0 */ + +#endif + +/*------------------------------------------------------------------------------ + * base register values for U8500 + */ +#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock Management Unit */ +#define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */ +#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ + +/* + * U8500 GPIO register base for 9 banks + */ +#define CFG_GPIO_0_BASE 0x8012E000 +#define CFG_GPIO_1_BASE 0x8012E080 +#define CFG_GPIO_2_BASE 0x8000E000 +#define CFG_GPIO_3_BASE 0x8000E080 +#define CFG_GPIO_4_BASE 0x8000E100 +#define CFG_GPIO_5_BASE 0x8000E180 +#define CFG_GPIO_6_BASE 0x8011E000 +#define CFG_GPIO_7_BASE 0x8011E080 +#define CFG_GPIO_8_BASE 0xA03FE000 + +/* + * U8500 I2C0 register base for SD card + */ +#define CFG_I2C0_BASE 0x80004000 + +/* + * U8500 RTC register base + */ +#define CFG_RTC_BASE 0x80154000 /* Real time clock */ + +#endif /* __CONFIG_H */ -- cgit v1.2.3