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authorDamien Lespiau <damien.lespiau@intel.com>2013-01-15 14:05:23 +0000
committerDamien Lespiau <damien.lespiau@intel.com>2013-03-04 15:54:36 +0000
commit31259c5edc51d16afcfd453f7abaf81601a62a15 (patch)
tree90cbdd1fc1810f00bbf50f90c0d5dc2f0355ddad
parente71f1d2ad46af09a61b0fd03f4b00514de5091e5 (diff)
assembler: Rename three_src_gen6 to da3src
Mesa's brw_structs.h has named/renamed this field to da3src. Sync with them. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
-rw-r--r--assembler/brw_structs.h6
-rw-r--r--assembler/gram.y30
2 files changed, 18 insertions, 18 deletions
diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h
index 59b28fae..e4fdb515 100644
--- a/assembler/brw_structs.h
+++ b/assembler/brw_structs.h
@@ -1142,7 +1142,7 @@ struct brw_instruction
GLuint dest_writemask:4;
GLuint dest_subreg_nr:3;
GLuint dest_reg_nr:8;
- } three_src_gen6; /* Three-source-operator instructions for Gen6+ */
+ } da3src;
struct
{
@@ -1229,7 +1229,7 @@ struct brw_instruction
GLuint src1_rep_ctrl:1;
GLuint src1_swizzle:8;
GLuint src1_subreg_nr_low:2; /* src1_subreg_nr spans on two DWORDs */
- } three_src_gen6; /* Three-source-operator instructions for Gen6+ */
+ } da3src;
struct
{
@@ -1315,7 +1315,7 @@ struct brw_instruction
GLuint src2_subreg_nr:3;
GLuint src2_reg_nr:8;
GLuint pad1:2; /* reserved */
- } three_src_gen6; /* Three-source-operator instructions for Gen6+ */
+ } da3src;
struct
{
diff --git a/assembler/gram.y b/assembler/gram.y
index a762835b..9380f445 100644
--- a/assembler/gram.y
+++ b/assembler/gram.y
@@ -797,8 +797,8 @@ trinaryinstruction:
$$.header.predicate_control = $1.header.predicate_control;
$$.header.predicate_inverse = $1.header.predicate_inverse;
- $$.bits1.three_src_gen6.flag_reg_nr = $1.bits2.da1.flag_reg_nr;
- $$.bits1.three_src_gen6.flag_subreg_nr = $1.bits2.da1.flag_subreg_nr;
+ $$.bits1.da3src.flag_reg_nr = $1.bits2.da1.flag_reg_nr;
+ $$.bits1.da3src.flag_subreg_nr = $1.bits2.da1.flag_subreg_nr;
$$.header.opcode = $2;
$$.header.destreg__conditionalmod = $3.cond;
@@ -3064,11 +3064,11 @@ static int reg_type_2_to_3(int reg_type)
int set_instruction_dest_three_src(struct brw_instruction *instr,
struct dst_operand *dest)
{
- instr->bits1.three_src_gen6.dest_reg_file = dest->reg_file;
- instr->bits1.three_src_gen6.dest_reg_nr = dest->reg_nr;
- instr->bits1.three_src_gen6.dest_subreg_nr = get_subreg_address(dest->reg_file, dest->reg_type, dest->subreg_nr, dest->address_mode) / 4; // in DWORD
- instr->bits1.three_src_gen6.dest_writemask = dest->writemask;
- instr->bits1.three_src_gen6.dest_reg_type = reg_type_2_to_3(dest->reg_type);
+ instr->bits1.da3src.dest_reg_file = dest->reg_file;
+ instr->bits1.da3src.dest_reg_nr = dest->reg_nr;
+ instr->bits1.da3src.dest_subreg_nr = get_subreg_address(dest->reg_file, dest->reg_type, dest->subreg_nr, dest->address_mode) / 4; // in DWORD
+ instr->bits1.da3src.dest_writemask = dest->writemask;
+ instr->bits1.da3src.dest_reg_type = reg_type_2_to_3(dest->reg_type);
return 0;
}
@@ -3079,9 +3079,9 @@ int set_instruction_src0_three_src(struct brw_instruction *instr,
reset_instruction_src_region(instr, src);
}
// TODO: supporting src0 swizzle, src0 modifier, src0 rep_ctrl
- instr->bits1.three_src_gen6.src_reg_type = reg_type_2_to_3(src->reg_type);
- instr->bits2.three_src_gen6.src0_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode) / 4; // in DWORD
- instr->bits2.three_src_gen6.src0_reg_nr = src->reg_nr;
+ instr->bits1.da3src.src_reg_type = reg_type_2_to_3(src->reg_type);
+ instr->bits2.da3src.src0_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode) / 4; // in DWORD
+ instr->bits2.da3src.src0_reg_nr = src->reg_nr;
return 0;
}
@@ -3093,9 +3093,9 @@ int set_instruction_src1_three_src(struct brw_instruction *instr,
}
// TODO: supporting src1 swizzle, src1 modifier, src1 rep_ctrl
int v = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode) / 4; // in DWORD
- instr->bits2.three_src_gen6.src1_subreg_nr_low = v % 4; // lower 2 bits
- instr->bits3.three_src_gen6.src1_subreg_nr_high = v / 4; // highest bit
- instr->bits3.three_src_gen6.src1_reg_nr = src->reg_nr;
+ instr->bits2.da3src.src1_subreg_nr_low = v % 4; // lower 2 bits
+ instr->bits3.da3src.src1_subreg_nr_high = v / 4; // highest bit
+ instr->bits3.da3src.src1_reg_nr = src->reg_nr;
return 0;
}
@@ -3106,8 +3106,8 @@ int set_instruction_src2_three_src(struct brw_instruction *instr,
reset_instruction_src_region(instr, src);
}
// TODO: supporting src2 swizzle, src2 modifier, src2 rep_ctrl
- instr->bits3.three_src_gen6.src2_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode) / 4; // in DWORD
- instr->bits3.three_src_gen6.src2_reg_nr = src->reg_nr;
+ instr->bits3.da3src.src2_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode) / 4; // in DWORD
+ instr->bits3.da3src.src2_reg_nr = src->reg_nr;
return 0;
}