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authorDamien Lespiau <damien.lespiau@intel.com>2013-12-06 16:07:22 -0800
committerDamien Lespiau <damien.lespiau@intel.com>2014-09-30 12:21:02 +0100
commit91ebcd0c54d365a633a7465a9d57f8c24c886af7 (patch)
tree8f605db2219fdd90ef1648cade4e1f83397b97d6
parent0eaa18061bee4b4b0c182d112db189019f01f49a (diff)
skl: Add SKL PCI ids
v2: Update to the latest PCI ids Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
-rw-r--r--lib/intel_chipset.h58
1 files changed, 52 insertions, 6 deletions
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 404c6325..e3ce603c 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -189,6 +189,22 @@ void intel_check_pch(void);
#define PCI_CHIP_CHERRYVIEW_2 0x22b2
#define PCI_CHIP_CHERRYVIEW_3 0x22b3
+#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916
+#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
+#define PCI_CHIP_SKYLAKE_ULT_GT3 0x1926
+#define PCI_CHIP_SKYLAKE_ULT_GT2F 0x1921
+#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E
+#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E
+#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912
+#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902
+#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B
+#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B
+#define PCI_CHIP_SKYLAKE_HALO_GT1 0x190B
+#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A
+#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192A
+#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A
+#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
+
#endif /* __GTK_DOC_IGNORE__ */
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
@@ -350,18 +366,44 @@ void intel_check_pch(void);
#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
IS_CHERRYVIEW(devid))
+#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
+ (devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
+ (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
+ (devid) == PCI_CHIP_SKYLAKE_HALO_GT1 || \
+ (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
+
+#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F || \
+ (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
+
+#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3 || \
+ (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \
+ (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
+
+#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \
+ IS_SKL_GT2(devid) || \
+ IS_SKL_GT3(devid))
+
+#define IS_GEN9(devid) IS_SKYLAKE(devid)
+
#define IS_965(devid) (IS_GEN4(devid) || \
IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_GEN7(devid) || \
- IS_GEN8(devid))
+ IS_GEN8(devid) || \
+ IS_GEN9(devid))
#define IS_9XX(devid) (IS_GEN3(devid) || \
IS_GEN4(devid) || \
IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_GEN7(devid) || \
- IS_GEN8(devid))
+ IS_GEN8(devid) || \
+ IS_GEN9(devid))
#define IS_INTEL(devid) (IS_GEN2(devid) || \
IS_GEN3(devid) || \
@@ -369,21 +411,25 @@ void intel_check_pch(void);
IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_GEN7(devid) || \
- IS_GEN8(devid))
+ IS_GEN8(devid) || \
+ IS_GEN9(devid))
#define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
- IS_GEN8(devid))
+ IS_GEN8(devid) || \
+ IS_GEN9(devid))
#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
IS_GEN7(devid) || \
- IS_GEN8(devid))
+ IS_GEN8(devid) || \
+ IS_GEN9(devid))
#define HAS_BSD_RING(devid) (IS_GEN5(devid) || \
IS_GEN6(devid) || \
IS_GEN7(devid) || \
- IS_GEN8(devid))
+ IS_GEN8(devid) || \
+ IS_GEN9(devid))
#define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \
(devid) == PCI_CHIP_I965_G_1 || \