quick_dump: A dump utility different than reg_dumper

This is the base tool for quick dump. At it's heart, quick dump is
simply a basic text parsing thingie which plugs into intel-gpu-tools to
do something similar to intel_reg_dumper.

The format for the register definition files is very open, so it's just
something simple for now.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

9 files changed, 314 insertions, 0 deletions

diff --git a/configure.ac b/configure.ac
index 13812796..15b0f88b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -140,6 +140,7 @@ AC_CONFIG_FILES([
 		 scripts/Makefile
 		 tests/Makefile
 		 tools/Makefile
+		 tools/quick_dump/Makefile
 		 debugger/Makefile
 		 debugger/system_routine/Makefile
 		 ])
diff --git a/tools/Makefile.am b/tools/Makefile.am
index 71fb087f..016fb890 100644
--- a/tools/Makefile.am
+++ b/tools/Makefile.am
@@ -1,3 +1,5 @@
+DIST_SUBDIRS = quick_dump
+
 bin_PROGRAMS = 				\
 	intel_disable_clock_gating 	\
 	intel_audio_dump 		\
diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am
new file mode 100644
index 00000000..34938c8e
--- /dev/null
+++ b/tools/quick_dump/Makefile.am
@@ -0,0 +1,3 @@
+EXTRA_DIST =  \
+	      base_display.txt base_interrupt.txt base_other.txt base_power.txt base_rings.txt \
+	      quick_dump.py
diff --git a/tools/quick_dump/base_display.txt b/tools/quick_dump/base_display.txt
new file mode 100644
index 00000000..8bead7f8
--- /dev/null
+++ b/tools/quick_dump/base_display.txt
@@ -0,0 +1,197 @@
+('CPU_VGACNTRL', '0x00041000', '')
+('PORT_DBG', '0x00042308', '')
+('DIGITAL_PORT_HOTPLUG_CNTRL', '0x00044030', '')
+('FDI_PLL_BIOS_0', '0x00046000', '')
+('FDI_PLL_BIOS_1', '0x00046004', '')
+('FDI_PLL_BIOS_2', '0x00046008', '')
+('DISPLAY_PORT_PLL_BIOS_0', '0x0004600c', '')
+('DISPLAY_PORT_PLL_BIOS_1', '0x00046010', '')
+('DISPLAY_PORT_PLL_BIOS_2', '0x00046014', '')
+('FDI_PLL_FREQ_CTL', '0x00046030', '')
+('BLC_PWM_CPU_CTL2', '0x00048250', '')
+('BLC_PWM_CPU_CTL', '0x00048254', '')
+('HTOTAL_A', '0x00060000', '')
+('HBLANK_A', '0x00060004', '')
+('HSYNC_A', '0x00060008', '')
+('VTOTAL_A', '0x0006000c', '')
+('VBLANK_A', '0x00060010', '')
+('VSYNC_A', '0x00060014', '')
+('PIPEASRC', '0x0006001c', '')
+('VSYNCSHIFT_A', '0x00060028', '')
+('PIPEA_DATA_M1', '0x00060030', '')
+('PIPEA_DATA_N1', '0x00060034', '')
+('PIPEA_DATA_M2', '0x00060038', '')
+('PIPEA_DATA_N2', '0x0006003c', '')
+('PIPEA_LINK_M1', '0x00060040', '')
+('PIPEA_LINK_N1', '0x00060044', '')
+('PIPEA_LINK_M2', '0x00060048', '')
+('PIPEA_LINK_N2', '0x0006004c', '')
+('FDI_TXA_CTL', '0x00060100', '')
+('HTOTAL_B', '0x00061000', '')
+('HBLANK_B', '0x00061004', '')
+('HSYNC_B', '0x00061008', '')
+('VTOTAL_B', '0x0006100c', '')
+('VBLANK_B', '0x00061010', '')
+('VSYNC_B', '0x00061014', '')
+('PIPEBSRC', '0x0006101c', '')
+('VSYNCSHIFT_B', '0x00061028', '')
+('PIPEB_DATA_M1', '0x00061030', '')
+('PIPEB_DATA_N1', '0x00061034', '')
+('PIPEB_DATA_M2', '0x00061038', '')
+('PIPEB_DATA_N2', '0x0006103c', '')
+('PIPEB_LINK_M1', '0x00061040', '')
+('PIPEB_LINK_N1', '0x00061044', '')
+('PIPEB_LINK_M2', '0x00061048', '')
+('PIPEB_LINK_N2', '0x0006104c', '')
+('FDI_TXB_CTL', '0x00061100', '')
+('HTOTAL_C', '0x00062000', '')
+('HBLANK_C', '0x00062004', '')
+('HSYNC_C', '0x00062008', '')
+('VTOTAL_C', '0x0006200c', '')
+('VBLANK_C', '0x00062010', '')
+('VSYNC_C', '0x00062014', '')
+('PIPECSRC', '0x0006201c', '')
+('VSYNCSHIFT_C', '0x00062028', '')
+('PIPEC_DATA_M1', '0x00062030', '')
+('PIPEC_DATA_N1', '0x00062034', '')
+('PIPEC_DATA_M2', '0x00062038', '')
+('PIPEC_DATA_N2', '0x0006203c', '')
+('PIPEC_LINK_M1', '0x00062040', '')
+('PIPEC_LINK_N1', '0x00062044', '')
+('PIPEC_LINK_M2', '0x00062048', '')
+('PIPEC_LINK_N2', '0x0006204c', '')
+('FDI_TXC_CTL', '0x00062100', '')
+('CPU_eDP_A', '0x00064000', '')
+('PFA_WIN_POS', '0x00068070', '')
+('PFA_WIN_SIZE', '0x00068074', '')
+('PFA_CTL_1', '0x00068080', '')
+('PFA_CTL_2', '0x00068084', '')
+('PFA_CTL_3', '0x00068088', '')
+('PFA_CTL_4', '0x00068090', '')
+('PFB_WIN_POS', '0x00068870', '')
+('PFB_WIN_SIZE', '0x00068874', '')
+('PFB_CTL_1', '0x00068880', '')
+('PFB_CTL_2', '0x00068884', '')
+('PFB_CTL_3', '0x00068888', '')
+('PFB_CTL_4', '0x00068890', '')
+('PFC_WIN_POS', '0x00069070', '')
+('PFC_WIN_SIZE', '0x00069074', '')
+('PFC_CTL_1', '0x00069080', '')
+('PFC_CTL_2', '0x00069084', '')
+('PFC_CTL_3', '0x00069088', '')
+('PFC_CTL_4', '0x00069090', '')
+('PIPEACONF', '0x00070008', '')
+('DSPACNTR', '0x00070180', '')
+('DSPABASE', '0x00070184', '')
+('DSPASTRIDE', '0x00070188', '')
+('DSPASURF', '0x0007019c', '')
+('DSPATILEOFF', '0x000701a4', '')
+('PIPEBCONF', '0x00071008', '')
+('DSPBCNTR', '0x00071180', '')
+('DSPBBASE', '0x00071184', '')
+('DSPBSTRIDE', '0x00071188', '')
+('DSPBSURF', '0x0007119c', '')
+('DSPBTILEOFF', '0x000711a4', '')
+('PIPECCONF', '0x00072008', '')
+('DSPCCNTR', '0x00072180', '')
+('DSPCBASE', '0x00072184', '')
+('DSPCSTRIDE', '0x00072188', '')
+('DSPCSURF', '0x0007219c', '')
+('DSPCTILEOFF', '0x000721a4', '')
+('PCH_DPLL_A', '0x000c6014', '')
+('PCH_DPLL_B', '0x000c6018', '')
+('PCH_FPA0', '0x000c6040', '')
+('PCH_FPA1', '0x000c6044', '')
+('PCH_FPB0', '0x000c6048', '')
+('PCH_FPB1', '0x000c604c', '')
+('PCH_DREF_CONTROL', '0x000c6200', '')
+('PCH_RAWCLK_FREQ', '0x000c6204', '')
+('PCH_DPLL_TMR_CFG', '0x000c6208', '')
+('PCH_SSC4_PARMS', '0x000c6210', '')
+('PCH_SSC4_AUX_PARMS', '0x000c6214', '')
+('PCH_DPLL_ANALOG_CTL', '0x000c6300', '')
+('PCH_DPLL_SEL', '0x000c7000', '')
+('PCH_PP_STATUS', '0x000c7200', '')
+('PCH_PP_CONTROL', '0x000c7204', '')
+('PCH_PP_ON_DELAYS', '0x000c7208', '')
+('PCH_PP_OFF_DELAYS', '0x000c720c', '')
+('PCH_PP_DIVISOR', '0x000c7210', '')
+('BLC_PWM_PCH_CTL1', '0x000c8250', '')
+('BLC_PWM_PCH_CTL2', '0x000c8254', '')
+('TRANS_HTOTAL_A', '0x000e0000', '')
+('TRANS_HBLANK_A', '0x000e0004', '')
+('TRANS_HSYNC_A', '0x000e0008', '')
+('TRANS_VTOTAL_A', '0x000e000c', '')
+('TRANS_VBLANK_A', '0x000e0010', '')
+('TRANS_VSYNC_A', '0x000e0014', '')
+('TRANS_VSYNCSHIFT_A', '0x000e0028', '')
+('TRANSA_DATA_M1', '0x000e0030', '')
+('TRANSA_DATA_N1', '0x000e0034', '')
+('TRANSA_DATA_M2', '0x000e0038', '')
+('TRANSA_DATA_N2', '0x000e003c', '')
+('TRANSA_DP_LINK_M1', '0x000e0040', '')
+('TRANSA_DP_LINK_N1', '0x000e0044', '')
+('TRANSA_DP_LINK_M2', '0x000e0048', '')
+('TRANSA_DP_LINK_N2', '0x000e004c', '')
+('TRANS_DP_CTL_A', '0x000e0300', '')
+('TRANS_HTOTAL_B', '0x000e1000', '')
+('TRANS_HBLANK_B', '0x000e1004', '')
+('TRANS_HSYNC_B', '0x000e1008', '')
+('TRANS_VTOTAL_B', '0x000e100c', '')
+('TRANS_VBLANK_B', '0x000e1010', '')
+('TRANS_VSYNC_B', '0x000e1014', '')
+('TRANS_VSYNCSHIFT_B', '0x000e1028', '')
+('TRANSB_DATA_M1', '0x000e1030', '')
+('TRANSB_DATA_N1', '0x000e1034', '')
+('TRANSB_DATA_M2', '0x000e1038', '')
+('TRANSB_DATA_N2', '0x000e103c', '')
+('TRANSB_DP_LINK_M1', '0x000e1040', '')
+('TRANSB_DP_LINK_N1', '0x000e1044', '')
+('TRANSB_DP_LINK_M2', '0x000e1048', '')
+('TRANSB_DP_LINK_N2', '0x000e104c', '')
+('PCH_ADPA', '0x000e1100', '')
+('HDMIB', '0x000e1140', '')
+('HDMIC', '0x000e1150', '')
+('HDMID', '0x000e1160', '')
+('PCH_LVDS', '0x000e1180', '')
+('TRANS_DP_CTL_B', '0x000e1300', '')
+('TRANS_HTOTAL_C', '0x000e2000', '')
+('TRANS_HBLANK_C', '0x000e2004', '')
+('TRANS_HSYNC_C', '0x000e2008', '')
+('TRANS_VTOTAL_C', '0x000e200c', '')
+('TRANS_VBLANK_C', '0x000e2010', '')
+('TRANS_VSYNC_C', '0x000e2014', '')
+('TRANS_VSYNCSHIFT_C', '0x000e2028', '')
+('TRANSC_DATA_M1', '0x000e2030', '')
+('TRANSC_DATA_N1', '0x000e2034', '')
+('TRANSC_DATA_M2', '0x000e2038', '')
+('TRANSC_DATA_N2', '0x000e203c', '')
+('TRANSC_DP_LINK_M1', '0x000e2040', '')
+('TRANSC_DP_LINK_N1', '0x000e2044', '')
+('TRANSC_DP_LINK_M2', '0x000e2048', '')
+('TRANSC_DP_LINK_N2', '0x000e204c', '')
+('TRANS_DP_CTL_C', '0x000e2300', '')
+('PCH_DP_B', '0x000e4100', '')
+('PCH_DP_C', '0x000e4200', '')
+('PCH_DP_D', '0x000e4300', '')
+('TRANSACONF', '0x000f0008', '')
+('FDI_RXA_CTL', '0x000f000c', '')
+('FDI_RXA_MISC', '0x000f0010', '')
+('FDI_RXA_IIR', '0x000f0014', '')
+('FDI_RXA_IMR', '0x000f0018', '')
+('FDI_RXA_TUSIZE1', '0x000f0030', '')
+('FDI_RXA_TUSIZE2', '0x000f0038', '')
+('TRANSBCONF', '0x000f1008', '')
+('FDI_RXB_CTL', '0x000f100c', '')
+('FDI_RXB_MISC', '0x000f1010', '')
+('FDI_RXB_IIR', '0x000f1014', '')
+('FDI_RXB_IMR', '0x000f1018', '')
+('FDI_RXB_TUSIZE1', '0x000f1030', '')
+('FDI_RXB_TUSIZE2', '0x000f1038', '')
+('TRANSCCONF', '0x000f2008', '')
+('FDI_RXC_CTL', '0x000f200c', '')
+('FDI_RXC_MISC', '0x000f2010', '')
+('FDI_RXC_TUSIZE1', '0x000f2030', '')
+('FDI_RXC_TUSIZE2', '0x000f2038', '')
+('FDI_PLL_CTL_1', '0x000fe000', '')
+('FDI_PLL_CTL_2', '0x000fe004', '')
diff --git a/tools/quick_dump/base_interrupt.txt b/tools/quick_dump/base_interrupt.txt
new file mode 100644
index 00000000..df4244ba
--- /dev/null
+++ b/tools/quick_dump/base_interrupt.txt
@@ -0,0 +1,20 @@
+('GEN6_PMINTRMSK', '0x0000a168', '')
+('DEISR', '0x00044000', '')
+('DEIMR', '0x00044004', '')
+('DEIIR', '0x00044008', '')
+('DEIER', '0x0004400c', '')
+('GTISR', '0x00044010', '')
+('GTIMR', '0x00044014', '')
+('GTIIR', '0x00044018', '')
+('GTIER', '0x0004401c', '')
+('GEN6_PMISR', '0x00044020', '')
+('GEN6_PMIMR', '0x00044024', '')
+('GEN6_PMIIR', '0x00044028', '')
+('GEN6_PMIER', '0x0004402c', '')
+('SDEISR', '0x000c4000', '')
+('SDEIMR', '0x000c4004', '')
+('SDEIIR', '0x000c4008', '')
+('SDEIER', '0x000c400c', '')
+('RENDER_IMR', '0x000020a8', '')
+('BSD_IMR', '0x000120a8', '')
+('BLT_IMR', '0x000220a8', '')
diff --git a/tools/quick_dump/base_other.txt b/tools/quick_dump/base_other.txt
new file mode 100644
index 00000000..24fefdf6
--- /dev/null
+++ b/tools/quick_dump/base_other.txt
@@ -0,0 +1,6 @@
+('PGETBL_CTL', '0x00002020', '')
+('MI_MODE', '0x0000209c', '')
+('ERROR_GEN6', '0x000040a0', '')
+('RENDER_HWSTAM', '0x00002098', '')
+('GEN6_BSD_HWSTAM', '0x00012098', '')
+('GEN6_BLITTER_HWSTAM', '0x00022098', '')
diff --git a/tools/quick_dump/base_power.txt b/tools/quick_dump/base_power.txt
new file mode 100644
index 00000000..4a142e52
--- /dev/null
+++ b/tools/quick_dump/base_power.txt
@@ -0,0 +1,21 @@
+('GEN6_RPNSWREQ', '0x0000a008', '')
+('GEN6_RC_VIDEO_FREQ', '0x0000a00c', '')
+('GEN6_RP_DOWN_TIMEOUT', '0x0000a010', '')
+('GEN6_RP_INTERRUPT_LIMITS', '0x0000a014', '')
+('GEN6_RP_CONTROL', '0x0000a024', '')
+('GEN6_RP_UP_THRESHOLD', '0x0000a02c', '')
+('GEN6_RP_UP_EI', '0x0000a068', '')
+('GEN6_RP_DOWN_EI', '0x0000a06c', '')
+('GEN6_RP_IDLE_HYSTERSIS', '0x0000a070', '')
+('GEN6_RC_CONTROL', '0x0000a090', '')
+('GEN6_RC_STATE', '0x0000a094', '')
+('GEN6_RC1_WAKE_RATE_LIMIT', '0x0000a098', '')
+('GEN6_RC6_WAKE_RATE_LIMIT', '0x0000a09c', '')
+('GEN6_RC_EVALUATION_INTERVAL', '0x0000a0a8', '')
+('GEN6_RC_IDLE_HYSTERSIS', '0x0000a0ac', '')
+('GEN6_RC_SLEEP', '0x0000a0b0', '')
+('GEN6_RC1e_THRESHOLD', '0x0000a0b4', '')
+('GEN6_RC6_THRESHOLD', '0x0000a0b8', '')
+('RC6_RESIDENCY_TIME', '0x00138108', '')
+('RC6p_RESIDENCY_TIME', '0x0013810c', '')
+('RC6pp_RESIDENCY_TIME', '0x00138110', '')
diff --git a/tools/quick_dump/base_rings.txt b/tools/quick_dump/base_rings.txt
new file mode 100644
index 00000000..d791172c
--- /dev/null
+++ b/tools/quick_dump/base_rings.txt
@@ -0,0 +1,27 @@
+('RENDER_INSTPM', '0x20c0', '')
+('BSD_INSTPM', '0x120c0', '')
+('BLT_INSTPM', '0x220c0', '')
+('RENDER_RING_HEAD', '0x2034', '')
+('BSD_RING_HEAD', '0x12034', '')
+('BLT_RING_HEAD', '0x22034', '')
+('RENDER_IPEIR', '0x2064', '')
+('BSD_IPEIR', '0x12064', '')
+('BLT_IPEIR', '0x22064', '')
+('RENDER_IPEHR', '0x2068', '')
+('BSD_IPEHR', '0x12068', '')
+('BLT_IPEHR', '0x22068', '')
+('RENDER_INSTDONE', '0x206c', '')
+('BSD_INSTDONE', '0x1206c', '')
+('BLT_INSTDONE', '0x2206c', '')
+('RENDER_INSTPS', '0x2070', '')
+('BSD_INSTPS', '0x12070', '')
+('BLT_INSTPS', '0x22070', '')
+('RENDER_RING_ACTHD', '0x2074', '')
+('BSD_RING_ACTHD', '0x12074', '')
+('BLT_RING_ACTHD', '0x22074', '')
+('RENDER_FADDR', '0x2078', '')
+('BSD_FADDR', '0x12078', '')
+('BLT_FADDR', '0x22078', '')
+('RENDER_RING_TAIL', '0x2030', '')
+('BSD_RING_TAIL', '0x12030', '')
+('BLT_RING_TAIL', '0x22030', '')
diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
new file mode 100755
index 00000000..3fea7bbe
--- /dev/null
+++ b/tools/quick_dump/quick_dump.py
@@ -0,0 +1,37 @@
+#!/usr/bin/env python3
+
+import argparse
+import os
+import sys
+import ast
+import subprocess
+
+def parse_file(file):
+	for line in file:
+		register = ast.literal_eval(line)
+		value = subprocess.check_output(["../intel_reg_read", register[1]])
+		value = value.decode('UTF-8') # convert the byte array to string
+		value = value.rstrip() #dump the newline
+		value = value.split(':') #output is 'addr : offset'
+		print(value[0], "(", register[0], ")", value[1])
+
+
+parser = argparse.ArgumentParser(description='Dumb register dumper.')
+parser.add_argument('-b', '--baseless', action='store_true', default=False, help='baseless mode, ignore files starting with base_')
+parser.add_argument('profile', nargs='?', type=argparse.FileType('r'), default=None)
+args = parser.parse_args()
+
+#parse anything named base_ these are assumed to apply for all gens.
+if args.baseless == False:
+	for root, dirs, files in os.walk('.'):
+		for name in files:
+			if name.startswith(("base_")):
+				file = open(name.rstrip(), 'r')
+				parse_file(file)
+
+if args.profile == None:
+	sys.exit()
+
+for extra in args.profile:
+	extra_file = open(extra.rstrip(), 'r')
+	parse_file(extra_file)