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| author | Zhao Yakui <yakui.zhao@intel.com> | 2013-04-09 09:59:15 +0800 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2013-11-06 09:39:41 -0800 |
| commit | 88e5f1fdf847a0ce284b8a01ff2cf3fb36e2b07c (patch) | |
| tree | 663ad36560500c38ec4ebb2cdfca2f7359d8fc02 /assembler/brw_defines.h | |
| parent | 60c9b41e11bf4a3ea4935bd30f5c169ca24de06d (diff) | |
assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8
Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
>add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw
>add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Diffstat (limited to 'assembler/brw_defines.h')
0 files changed, 0 insertions, 0 deletions