diff options
| author | Zhao Yakui <yakui.zhao@intel.com> | 2013-04-09 09:59:15 +0800 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2013-11-06 09:39:41 -0800 |
| commit | 88e5f1fdf847a0ce284b8a01ff2cf3fb36e2b07c (patch) | |
| tree | 663ad36560500c38ec4ebb2cdfca2f7359d8fc02 /assembler/gram.y | |
| parent | 60c9b41e11bf4a3ea4935bd30f5c169ca24de06d (diff) | |
assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8
Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
>add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw
>add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Diffstat (limited to 'assembler/gram.y')
| -rw-r--r-- | assembler/gram.y | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/assembler/gram.y b/assembler/gram.y index 5671a0f4..03f1be64 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -294,6 +294,12 @@ static bool validate_dst_reg(struct brw_program_instruction *insn, struct brw_re return false; } + if (reg->address_mode == BRW_ADDRESS_REGISTER_INDIRECT_REGISTER && + access_mode(insn) == BRW_ALIGN_16) { + fprintf(stderr, "error: indirect Dst addr mode in align16 instruction\n"); + return false; + } + return true; } @@ -317,6 +323,12 @@ static bool validate_src_reg(struct brw_program_instruction *insn, return false; } + if (reg.address_mode == BRW_ADDRESS_REGISTER_INDIRECT_REGISTER && + access_mode(insn) == BRW_ALIGN_16) { + fprintf(stderr, "error: indirect Source addr mode in align16 instruction\n"); + return false; + } + assert(reg.hstride >= 0 && reg.hstride < ARRAY_SIZE(hstride_for_reg)); hstride = hstride_for_reg[reg.hstride]; |