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authorEric Anholt <eric@anholt.net>2006-08-25 09:46:18 -0700
committerDamien Lespiau <damien.lespiau@intel.com>2013-03-04 15:54:22 +0000
commit569990bf6b6f1d95ffa88981d0afe8b16626e4be (patch)
tree42c1739546855837cab48d806f21d26eb3750413 /assembler
parent3d36079ae3f9cab993b7bbec68f6fa2fbfb60136 (diff)
Lex the register number with the register name.
This avoids the need for a start condition to prevent for example g1.8<0,1,0>UW being lexed as GENREG NUMBER LANGLE etc. rather than GENREG INTEGER DOT INTEGER LANGLE etc.
Diffstat (limited to 'assembler')
-rw-r--r--assembler/gram.y32
-rw-r--r--assembler/lex.l41
2 files changed, 38 insertions, 35 deletions
diff --git a/assembler/gram.y b/assembler/gram.y
index 0609d90a..7ed2f41b 100644
--- a/assembler/gram.y
+++ b/assembler/gram.y
@@ -63,7 +63,8 @@
%token <integer> ALIGN1 ALIGN16 MASK_DISABLE EOT
-%token GENREG MSGREG ACCREG ADDRESSREG FLAGREG CONTROLREG IPREG
+%token <integer> GENREG MSGREG ACCREG ADDRESSREG
+%token FLAGREG CONTROLREG IPREG
%token MOV
%token MUL MAC MACH LINE SAD2 SADA2 DP4 DPH DP3 DP2
@@ -497,46 +498,51 @@ subregnum: DOT INTEGER
;
/* 1.4.5: Register files and register numbers */
-directgenreg: GENREG INTEGER subregnum
+directgenreg: GENREG subregnum
{
/* Returns an instruction with just the destination register
* fields filled in.
*/
$$.reg_file = BRW_GENERAL_REGISTER_FILE;
- $$.reg_nr = $2;
- $$.subreg_nr = $3;
+ $$.reg_nr = $1;
+ $$.subreg_nr = $2;
}
-directmsgreg: MSGREG INTEGER subregnum
+directmsgreg: MSGREG subregnum
{
/* Returns an instruction with just the destination register
* fields filled in.
*/
$$.reg_file = BRW_MESSAGE_REGISTER_FILE;
- $$.reg_nr = $2;
- $$.subreg_nr = $3;
+ $$.reg_nr = $1;
+ $$.subreg_nr = $2;
}
;
-accreg: ACCREG INTEGER subregnum
+accreg: ACCREG subregnum
{
/* Returns an instruction with just the destination register
* fields filled in.
*/
+ if ($1 > 1) {
+ fprintf(stderr,
+ "accumulator register number %d out of range", $1);
+ YYERROR;
+ }
$$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
- $$.reg_nr = BRW_ARF_ACCUMULATOR | $2;
- $$.subreg_nr = $3;
+ $$.reg_nr = BRW_ARF_ACCUMULATOR | $1;
+ $$.subreg_nr = $2;
}
;
-addrreg: ADDRESSREG INTEGER subregnum
+addrreg: ADDRESSREG subregnum
{
/* Returns an instruction with just the destination register
* fields filled in.
*/
$$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
- $$.reg_nr = BRW_ARF_ADDRESS | $2;
- $$.subreg_nr = $3;
+ $$.reg_nr = BRW_ARF_ADDRESS | $1;
+ $$.subreg_nr = $2;
}
;
diff --git a/assembler/lex.l b/assembler/lex.l
index 8982df55..e60b228b 100644
--- a/assembler/lex.l
+++ b/assembler/lex.l
@@ -7,7 +7,6 @@
int saved_state = INITIAL;
%}
-%s IN_REG
%x BLOCK_COMMENT
%%
@@ -74,33 +73,31 @@ int saved_state = INITIAL;
"-" { return MINUS; }
"(abs)" { return ABS; }
- /* XXX: this lexing of register files is shady */
-"acc" {
- BEGIN(IN_REG);
+"acc"[0-9]+ {
+ yylval.integer = atoi(yytext + 1);
return ACCREG;
}
-"a" {
- BEGIN(IN_REG);
+"a"[0-9]+ {
+ yylval.integer = atoi(yytext + 1);
return ADDRESSREG;
}
-"m" {
- BEGIN(IN_REG);
+"m"[0-9]+ {
+ yylval.integer = atoi(yytext + 1);
return MSGREG;
}
-"f" {
- BEGIN(IN_REG);
+"f"[0-9]+ {
+ yylval.integer = atoi(yytext + 1);
return FLAGREG;
}
-[gr] {
- BEGIN(IN_REG);
+[gr][0-9]+ {
+ yylval.integer = atoi(yytext + 1);
return GENREG;
}
-"cr" {
- BEGIN(IN_REG);
+"cr"[0-9]+ {
+ yylval.integer = atoi(yytext + 1);
return CONTROLREG;
}
"ip" {
- BEGIN(IN_REG);
return IPREG;
}
@@ -108,13 +105,13 @@ int saved_state = INITIAL;
* Lexing of register types should probably require the ":" symbol specified
* in the BNF of the assembly, but our existing source didn't use that syntax.
*/
-"UD" { BEGIN(INITIAL); return TYPE_UD; }
-"D" { BEGIN(INITIAL); return TYPE_D; }
-"UW" { BEGIN(INITIAL); return TYPE_UW; }
-"W" { BEGIN(INITIAL); return TYPE_W; }
-"UB" { BEGIN(INITIAL); return TYPE_UB; }
-"B" { BEGIN(INITIAL); return TYPE_B; }
-"F" { BEGIN(INITIAL); return TYPE_F; }
+"UD" { return TYPE_UD; }
+"D" { return TYPE_D; }
+"UW" { return TYPE_UW; }
+"W" { return TYPE_W; }
+"UB" { return TYPE_UB; }
+"B" { return TYPE_B; }
+"F" { return TYPE_F; }
"sat" { return SATURATE; }
"align1" { return ALIGN1; }