diff options
| author | Damien Lespiau <damien.lespiau@intel.com> | 2013-01-31 18:22:49 +0000 |
|---|---|---|
| committer | Damien Lespiau <damien.lespiau@intel.com> | 2013-03-04 15:54:42 +0000 |
| commit | fa2b679cc926add04c22c1e5ffb32bf9d9bd8584 (patch) | |
| tree | 24bdf026c88de4e41712d0aa1299d16102db5d8e /assembler | |
| parent | 28ff66a13c9dcc7aeb7bcff8d173495ee53deef9 (diff) | |
assembler: Use set_instruction_src1() in send
No reason not to!
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Diffstat (limited to 'assembler')
| -rw-r--r-- | assembler/gram.y | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/assembler/gram.y b/assembler/gram.y index cd420048..d69d7b4c 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -1200,9 +1200,8 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget YYERROR; if (set_instruction_src0(&$$, &$6, &@6) != 0) YYERROR; - GEN(&$$)->bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; - GEN(&$$)->bits1.da1.src1_reg_type = $7.reg.type; - GEN(&$$)->bits3.ud = $7.reg.dw1.ud; + if (set_instruction_src1(&$$, &$7, &@7) != 0) + YYERROR; } | predicate SEND execsize dst sendleadreg sndopr imm32reg instoptions { @@ -1241,10 +1240,8 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget src0.reg.nr = $5.nr; src0.reg.subnr = 0; set_instruction_src0(&$$, &src0, NULL); + set_instruction_src1(&$$, &$7, NULL); - GEN(&$$)->bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; - GEN(&$$)->bits1.da1.src1_reg_type = $7.reg.type; - GEN(&$$)->bits3.ud = $7.reg.dw1.ud; GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); } | predicate SEND execsize dst sendleadreg sndopr directsrcoperand instoptions @@ -1306,15 +1303,13 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget YYERROR; if (set_instruction_src0(&$$, &$6, &@6) != 0) YYERROR; - GEN(&$$)->bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; - GEN(&$$)->bits1.da1.src1_reg_type = $8.reg.type; + if (set_instruction_src1(&$$, &$8, &@8) != 0) + YYERROR; + if (IS_GENx(5)) { GEN(&$$)->bits2.send_gen5.sfid = ($7 & EX_DESC_SFID_MASK); - GEN(&$$)->bits3.ud = $8.reg.dw1.ud; GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($7 & EX_DESC_EOT_MASK); } - else - GEN(&$$)->bits3.ud = $8.reg.dw1.ud; } | predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions { |