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authorLionel Landwerlin <lionel.g.landwerlin@intel.com>2017-12-14 17:55:04 +0000
committerLionel Landwerlin <lionel.g.landwerlin@intel.com>2018-03-12 12:34:56 +0000
commitba5f960ea15b554e565ae38b319e8c80b2e2c8b6 (patch)
tree5f32a70c673c6a3761dafd5056604fa481e83ef1 /include/drm-uapi/amdgpu_drm.h
parentd7fcd3382e4ca141171db1c2c415150e2cac082f (diff)
include: bump drm uAPI headers
Taken from drm-tip : commit 1e6aa7e55c28ecd842b8b4599e4273c2429ee061 Author: Jani Nikula <jani.nikula@intel.com> Date: Tue Mar 6 12:41:55 2018 +0200 drm/i915/icl: do not save DDI A/E sharing bit for ICL Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Diffstat (limited to 'include/drm-uapi/amdgpu_drm.h')
-rw-r--r--include/drm-uapi/amdgpu_drm.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index 4d21191a..1816bd82 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -664,6 +664,10 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_SENSOR_VDDNB 0x6
/* Subquery id: Query graphics voltage */
#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
+ /* Subquery id: Query GPU stable pstate shader clock */
+ #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
+ /* Subquery id: Query GPU stable pstate memory clock */
+ #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
/* Number of VRAM page faults on CPU access. */
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F