diff options
author | Lukasz Kalamarz <lukasz.kalamarz@intel.com> | 2018-11-29 13:57:25 +0100 |
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committer | Katarzyna Dec <katarzyna.dec@intel.com> | 2018-12-04 13:50:23 +0100 |
commit | 6a965853560b2f8070d639b61506506842f87ff5 (patch) | |
tree | 8b19dbe21598fcbf060f9baecd619962a73e9c39 /include/drm-uapi/i915_drm.h | |
parent | 14c1b132c8f829637c55fb071a9a2e5ce00e7ed8 (diff) |
include/drm-uapi: bump headers
Taken from drm-next :
commit 1ec28f8b8ada4e4f77d1af006a3a474f4f83b8e3
Merge: 61647c77cb15 2e6e902d1850
Author: Dave Airlie <airlied@redhat.com>
Date: Thu Nov 29 10:34:03 2018 +1000
Merge v4.20-rc4 into drm-next
Generated by 'make headers_install'
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Diffstat (limited to 'include/drm-uapi/i915_drm.h')
-rw-r--r-- | include/drm-uapi/i915_drm.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h index 16e452aa..e39b26d4 100644 --- a/include/drm-uapi/i915_drm.h +++ b/include/drm-uapi/i915_drm.h @@ -412,6 +412,14 @@ typedef struct drm_i915_irq_wait { int irq_seq; } drm_i915_irq_wait_t; +/* + * Different modes of per-process Graphics Translation Table, + * see I915_PARAM_HAS_ALIASING_PPGTT + */ +#define I915_GEM_PPGTT_NONE 0 +#define I915_GEM_PPGTT_ALIASING 1 +#define I915_GEM_PPGTT_FULL 2 + /* Ioctl to query kernel params: */ #define I915_PARAM_IRQ_ACTIVE 1 @@ -529,6 +537,28 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 +/* + * Once upon a time we supposed that writes through the GGTT would be + * immediately in physical memory (once flushed out of the CPU path). However, + * on a few different processors and chipsets, this is not necessarily the case + * as the writes appear to be buffered internally. Thus a read of the backing + * storage (physical memory) via a different path (with different physical tags + * to the indirect write via the GGTT) will see stale values from before + * the GGTT write. Inside the kernel, we can for the most part keep track of + * the different read/write domains in use (e.g. set-domain), but the assumption + * of coherency is baked into the ABI, hence reporting its true state in this + * parameter. + * + * Reports true when writes via mmap_gtt are immediately visible following an + * lfence to flush the WCB. + * + * Reports false when writes via mmap_gtt are indeterminately delayed in an in + * internal buffer and are _not_ immediately visible to third parties accessing + * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC + * communications channel when reporting false is strongly disadvised. + */ +#define I915_PARAM_MMAP_GTT_COHERENT 52 + typedef struct drm_i915_getparam { __s32 param; /* |