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authorMaarten Lankhorst <maarten.lankhorst@linux.intel.com>2019-02-01 11:13:59 +0100
committerMaarten Lankhorst <maarten.lankhorst@linux.intel.com>2019-02-13 13:02:06 +0100
commitcb8e45a624426648ddffc675c8232eb31e58a50e (patch)
tree091016991391971a393efabdb50e0f65b13e3a9c /include
parentb0033d9310c13eee8fd8268ec0ea16af91c92e6e (diff)
lib/igt_fb: Add support for P01x formats, v5.
The P01x formats are planar 16 bits per component, with the unused lower bits set to 0. This means they can all be converted the same way. Only the range is slightly different, and this is handled in the color_encoding implementation. This requires cairo 1.17.2 and pixman 0.36. This works but doesn't give extra precision. For more than 8 bits precision a few more patches are required to pixman, pending review: https://lists.freedesktop.org/archives/pixman/2019-January/004815.html https://lists.freedesktop.org/archives/pixman/2019-January/004809.html Once those are merged, we will require the next pixman release for better precision. Changes since v1: - Add fallback color definitions when compiling on cairo version < 1.17.2. - Skip when FB creation fails on HDR formats, instead of failing. Changes since v2: - Complain slightly harder when pixman/cairo are out of date. - Create a fb with alpha when converting to pixman formats with alpha. - Oops, s/pixman_format_code_t/cairo_format_t/ Changes since v3: - Rebase on top of upstream YUV changes. Changes since v4: - Rebase again. - Use drm_fourcc.h from drm-misc-next. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> #v4
Diffstat (limited to 'include')
-rw-r--r--include/drm-uapi/drm_fourcc.h40
1 files changed, 40 insertions, 0 deletions
diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index 41106c83..bab20298 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -196,6 +196,27 @@ extern "C" {
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [10:6] little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
+ */
+#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y:x [12:4] little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
+ */
+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
+
+/*
+ * 2 plane YCbCr MSB aligned
+ * index 0 = Y plane, [15:0] Y little endian
+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
+ */
+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
@@ -238,6 +259,8 @@ extern "C" {
#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
+#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
+
/* add more to the end as needed */
#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
@@ -572,6 +595,9 @@ extern "C" {
* AFBC has several features which may be supported and/or used, which are
* represented using bits in the modifier. Not all combinations are valid,
* and different devices or use-cases may support different combinations.
+ *
+ * Further information on the use of AFBC modifiers can be found in
+ * Documentation/gpu/afbc.rst
*/
#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
@@ -667,6 +693,20 @@ extern "C" {
*/
#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
+/*
+ * Allwinner tiled modifier
+ *
+ * This tiling mode is implemented by the VPU found on all Allwinner platforms,
+ * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
+ * planes.
+ *
+ * With this tiling, the luminance samples are disposed in tiles representing
+ * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
+ * The pixel order in each tile is linear and the tiles are disposed linearly,
+ * both in row-major order.
+ */
+#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
+
#if defined(__cplusplus)
}
#endif