diff options
| author | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2016-12-20 13:45:25 +0200 |
|---|---|---|
| committer | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2017-01-03 13:42:37 +0200 |
| commit | 770fd185eb7c878d7d1e16af4aa4f456a264d148 (patch) | |
| tree | 7e4d439a9237d5b497f15d33bd4842e339d7f338 /lib/i915_pciids.h | |
| parent | e5e8b7cecc5a03f4db5ec4a63e9bea28fd125e9b (diff) | |
lib/i915_pciids.h: Update to latest version wich includes GLK ids
Copy the include/drm/i915_pciids.h file from following kernel commit,
which includes Geminilake PCI IDs.
commit 8363e3c3947d0e22955f94a6a87e4f17ce5087b4
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date: Thu Nov 10 17:23:08 2016 +0200
drm/i915/glk: Add Geminilake PCI IDs
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Diffstat (limited to 'lib/i915_pciids.h')
| -rw-r--r-- | lib/i915_pciids.h | 42 |
1 files changed, 18 insertions, 24 deletions
diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h index 33466bfc..540be9ff 100644 --- a/lib/i915_pciids.h +++ b/lib/i915_pciids.h @@ -134,7 +134,7 @@ #define INTEL_IVB_Q_IDS(info) \ INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ -#define INTEL_HSW_D_IDS(info) \ +#define INTEL_HSW_IDS(info) \ INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ @@ -179,9 +179,7 @@ INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \ - -#define INTEL_HSW_M_IDS(info) \ + INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ @@ -198,17 +196,15 @@ INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ -#define INTEL_VLV_M_IDS(info) \ +#define INTEL_VLV_IDS(info) \ INTEL_VGA_DEVICE(0x0f30, info), \ INTEL_VGA_DEVICE(0x0f31, info), \ INTEL_VGA_DEVICE(0x0f32, info), \ INTEL_VGA_DEVICE(0x0f33, info), \ - INTEL_VGA_DEVICE(0x0157, info) - -#define INTEL_VLV_D_IDS(info) \ + INTEL_VGA_DEVICE(0x0157, info), \ INTEL_VGA_DEVICE(0x0155, info) -#define INTEL_BDW_GT12M_IDS(info) \ +#define INTEL_BDW_GT12_IDS(info) \ INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ @@ -216,21 +212,17 @@ INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ - INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */ - -#define INTEL_BDW_GT12D_IDS(info) \ + INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \ INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ -#define INTEL_BDW_GT3M_IDS(info) \ +#define INTEL_BDW_GT3_IDS(info) \ INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \ INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \ - INTEL_VGA_DEVICE(0x162E, info) /* ULX */ - -#define INTEL_BDW_GT3D_IDS(info) \ + INTEL_VGA_DEVICE(0x162E, info), /* ULX */\ INTEL_VGA_DEVICE(0x162A, info), /* Server */ \ INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ @@ -244,14 +236,12 @@ INTEL_VGA_DEVICE(0x163A, info), /* Server */ \ INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ -#define INTEL_BDW_M_IDS(info) \ - INTEL_BDW_GT12M_IDS(info), \ - INTEL_BDW_GT3M_IDS(info), \ - INTEL_BDW_RSVDM_IDS(info) - -#define INTEL_BDW_D_IDS(info) \ - INTEL_BDW_GT12D_IDS(info), \ - INTEL_BDW_GT3D_IDS(info), \ +#define INTEL_BDW_IDS(info) \ + INTEL_BDW_GT12_IDS(info), \ + INTEL_BDW_GT3_IDS(info), \ + INTEL_BDW_RSVDM_IDS(info), \ + INTEL_BDW_GT12_IDS(info), \ + INTEL_BDW_GT3_IDS(info), \ INTEL_BDW_RSVDD_IDS(info) #define INTEL_CHV_IDS(info) \ @@ -302,6 +292,10 @@ INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \ INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */ +#define INTEL_GLK_IDS(info) \ + INTEL_VGA_DEVICE(0x3184, info), \ + INTEL_VGA_DEVICE(0x3185, info) + #define INTEL_KBL_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \ INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \ |