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authorRodrigo Vivi <rodrigo.vivi@intel.com>2019-02-01 23:32:31 -0800
committerRodrigo Vivi <rodrigo.vivi@intel.com>2019-02-04 10:16:25 -0800
commitb2920f54dc410d5fde705713c7d7eb76ae23dc1a (patch)
treef9c48d7a345ffad9b5d2f64422fbcf7bafb64337 /lib/i915_pciids.h
parentcfc9ee5ba55f4d37af81f61f3ff80da5eac75a08 (diff)
lib: sync i915_pciids.h with kernel
Add more PCI Device IDs for Coffee Lake and Ice Lake. Align with kernel commits: 5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.") 03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake") Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Diffstat (limited to 'lib/i915_pciids.h')
-rw-r--r--lib/i915_pciids.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
index 19266714..d2fad7b0 100644
--- a/lib/i915_pciids.h
+++ b/lib/i915_pciids.h
@@ -394,6 +394,9 @@
INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
/* CFL H */
+#define INTEL_CFL_H_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x3E9C, info)
+
#define INTEL_CFL_H_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
@@ -426,6 +429,7 @@
#define INTEL_CFL_IDS(info) \
INTEL_CFL_S_GT1_IDS(info), \
INTEL_CFL_S_GT2_IDS(info), \
+ INTEL_CFL_H_GT1_IDS(info), \
INTEL_CFL_H_GT2_IDS(info), \
INTEL_CFL_U_GT2_IDS(info), \
INTEL_CFL_U_GT3_IDS(info), \
@@ -457,9 +461,13 @@
INTEL_VGA_DEVICE(0x8A51, info), \
INTEL_VGA_DEVICE(0x8A5C, info), \
INTEL_VGA_DEVICE(0x8A5D, info), \
+ INTEL_VGA_DEVICE(0x8A59, info), \
+ INTEL_VGA_DEVICE(0x8A58, info), \
INTEL_VGA_DEVICE(0x8A52, info), \
INTEL_VGA_DEVICE(0x8A5A, info), \
INTEL_VGA_DEVICE(0x8A5B, info), \
+ INTEL_VGA_DEVICE(0x8A57, info), \
+ INTEL_VGA_DEVICE(0x8A56, info), \
INTEL_VGA_DEVICE(0x8A71, info), \
INTEL_VGA_DEVICE(0x8A70, info)