intel_chipset: Remove unused PCI_CHIP ids

These are now taken from i915_pciids.h. However, some of the older ids
are still used explicitly for per-devid information, and so are not yet
removable.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

1 files changed, 0 insertions, 150 deletions

diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 42343614..1716b835 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -105,13 +105,6 @@ void intel_check_pch(void);
 #define PCI_CHIP_I945_GM		0x27A2
 #define PCI_CHIP_I945_GME		0x27AE
 
-#define PCI_CHIP_Q35_G			0x29B2
-#define PCI_CHIP_G33_G			0x29C2
-#define PCI_CHIP_Q33_G			0x29D2
-
-#define PCI_CHIP_IGD_GM			0xA011
-#define PCI_CHIP_IGD_G			0xA001
-
 #define PCI_CHIP_I965_G			0x29A2
 #define PCI_CHIP_I965_Q			0x2992
 #define PCI_CHIP_I965_G_1		0x2982
@@ -121,153 +114,10 @@ void intel_check_pch(void);
 
 #define PCI_CHIP_GM45_GM		0x2A42
 
-#define PCI_CHIP_IGD_E_G		0x2E02
 #define PCI_CHIP_Q45_G			0x2E12
 #define PCI_CHIP_G45_G			0x2E22
 #define PCI_CHIP_G41_G			0x2E32
 
-#define PCI_CHIP_ILD_G			0x0042
-#define PCI_CHIP_ILM_G			0x0046
-
-#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102 /* desktop */
-#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
-#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
-#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106 /* mobile */
-#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
-#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
-#define PCI_CHIP_SANDYBRIDGE_S		0x010A /* server */
-
-#define PCI_CHIP_IVYBRIDGE_GT1		0x0152 /* desktop */
-#define PCI_CHIP_IVYBRIDGE_GT2		0x0162
-#define PCI_CHIP_IVYBRIDGE_M_GT1	0x0156 /* mobile */
-#define PCI_CHIP_IVYBRIDGE_M_GT2	0x0166
-#define PCI_CHIP_IVYBRIDGE_S		0x015a /* server */
-#define PCI_CHIP_IVYBRIDGE_S_GT2	0x016a /* server */
-
-#define PCI_CHIP_HASWELL_GT1		0x0402 /* Desktop */
-#define PCI_CHIP_HASWELL_GT2		0x0412
-#define PCI_CHIP_HASWELL_GT3		0x0422
-#define PCI_CHIP_HASWELL_M_GT1		0x0406 /* Mobile */
-#define PCI_CHIP_HASWELL_M_GT2		0x0416
-#define PCI_CHIP_HASWELL_M_GT3		0x0426
-#define PCI_CHIP_HASWELL_S_GT1		0x040A /* Server */
-#define PCI_CHIP_HASWELL_S_GT2		0x041A
-#define PCI_CHIP_HASWELL_S_GT3		0x042A
-#define PCI_CHIP_HASWELL_B_GT1		0x040B /* Reserved */
-#define PCI_CHIP_HASWELL_B_GT2		0x041B
-#define PCI_CHIP_HASWELL_B_GT3		0x042B
-#define PCI_CHIP_HASWELL_E_GT1		0x040E /* Reserved */
-#define PCI_CHIP_HASWELL_E_GT2		0x041E
-#define PCI_CHIP_HASWELL_E_GT3		0x042E
-#define PCI_CHIP_HASWELL_SDV_GT1	0x0C02 /* Desktop */
-#define PCI_CHIP_HASWELL_SDV_GT2	0x0C12
-#define PCI_CHIP_HASWELL_SDV_GT3	0x0C22
-#define PCI_CHIP_HASWELL_SDV_M_GT1	0x0C06 /* Mobile */
-#define PCI_CHIP_HASWELL_SDV_M_GT2	0x0C16
-#define PCI_CHIP_HASWELL_SDV_M_GT3	0x0C26
-#define PCI_CHIP_HASWELL_SDV_S_GT1	0x0C0A /* Server */
-#define PCI_CHIP_HASWELL_SDV_S_GT2	0x0C1A
-#define PCI_CHIP_HASWELL_SDV_S_GT3	0x0C2A
-#define PCI_CHIP_HASWELL_SDV_B_GT1	0x0C0B /* Reserved */
-#define PCI_CHIP_HASWELL_SDV_B_GT2	0x0C1B
-#define PCI_CHIP_HASWELL_SDV_B_GT3	0x0C2B
-#define PCI_CHIP_HASWELL_SDV_E_GT1	0x0C0E /* Reserved */
-#define PCI_CHIP_HASWELL_SDV_E_GT2	0x0C1E
-#define PCI_CHIP_HASWELL_SDV_E_GT3	0x0C2E
-#define PCI_CHIP_HASWELL_ULT_GT1	0x0A02 /* Desktop */
-#define PCI_CHIP_HASWELL_ULT_GT2	0x0A12
-#define PCI_CHIP_HASWELL_ULT_GT3	0x0A22
-#define PCI_CHIP_HASWELL_ULT_M_GT1	0x0A06 /* Mobile */
-#define PCI_CHIP_HASWELL_ULT_M_GT2	0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT3	0x0A26
-#define PCI_CHIP_HASWELL_ULT_S_GT1	0x0A0A /* Server */
-#define PCI_CHIP_HASWELL_ULT_S_GT2	0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT3	0x0A2A
-#define PCI_CHIP_HASWELL_ULT_B_GT1	0x0A0B /* Reserved */
-#define PCI_CHIP_HASWELL_ULT_B_GT2	0x0A1B
-#define PCI_CHIP_HASWELL_ULT_B_GT3	0x0A2B
-#define PCI_CHIP_HASWELL_ULT_E_GT1	0x0A0E /* Reserved */
-#define PCI_CHIP_HASWELL_ULT_E_GT2	0x0A1E
-#define PCI_CHIP_HASWELL_ULT_E_GT3	0x0A2E
-#define PCI_CHIP_HASWELL_CRW_GT1	0x0D02 /* Desktop */
-#define PCI_CHIP_HASWELL_CRW_GT2	0x0D12
-#define PCI_CHIP_HASWELL_CRW_GT3	0x0D22
-#define PCI_CHIP_HASWELL_CRW_M_GT1	0x0D06 /* Mobile */
-#define PCI_CHIP_HASWELL_CRW_M_GT2	0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT3	0x0D26
-#define PCI_CHIP_HASWELL_CRW_S_GT1	0x0D0A /* Server */
-#define PCI_CHIP_HASWELL_CRW_S_GT2	0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT3	0x0D2A
-#define PCI_CHIP_HASWELL_CRW_B_GT1	0x0D0B /* Reserved */
-#define PCI_CHIP_HASWELL_CRW_B_GT2	0x0D1B
-#define PCI_CHIP_HASWELL_CRW_B_GT3	0x0D2B
-#define PCI_CHIP_HASWELL_CRW_E_GT1	0x0D0E /* Reserved */
-#define PCI_CHIP_HASWELL_CRW_E_GT2	0x0D1E
-#define PCI_CHIP_HASWELL_CRW_E_GT3	0x0D2E
-#define BDW_SPARE 0x2
-#define BDW_ULT 0x6
-#define BDW_HALO 0xb
-#define BDW_SERVER 0xa
-#define BDW_WORKSTATION 0xd
-#define BDW_ULX 0xe
-
-#define PCI_CHIP_VALLEYVIEW_PO		0x0f30 /* VLV PO board */
-#define PCI_CHIP_VALLEYVIEW_1		0x0f31
-#define PCI_CHIP_VALLEYVIEW_2		0x0f32
-#define PCI_CHIP_VALLEYVIEW_3		0x0f33
-
-#define PCI_CHIP_CHERRYVIEW_0		0x22b0
-#define PCI_CHIP_CHERRYVIEW_1		0x22b1
-#define PCI_CHIP_CHERRYVIEW_2		0x22b2
-#define PCI_CHIP_CHERRYVIEW_3		0x22b3
-
-#define PCI_CHIP_SKYLAKE_ULT_GT2	0x1916
-#define PCI_CHIP_SKYLAKE_ULT_GT1	0x1906
-#define PCI_CHIP_SKYLAKE_ULT_GT3	0x1926
-#define PCI_CHIP_SKYLAKE_ULT_GT2F	0x1921
-#define PCI_CHIP_SKYLAKE_ULX_GT1	0x190E
-#define PCI_CHIP_SKYLAKE_ULX_GT2	0x191E
-#define PCI_CHIP_SKYLAKE_DT_GT2		0x1912
-#define PCI_CHIP_SKYLAKE_DT_GT1		0x1902
-#define PCI_CHIP_SKYLAKE_DT_GT4		0x1932
-#define PCI_CHIP_SKYLAKE_HALO_GT2	0x191B
-#define PCI_CHIP_SKYLAKE_HALO_GT3	0x192B
-#define PCI_CHIP_SKYLAKE_HALO_GT1 	0x190B
-#define PCI_CHIP_SKYLAKE_HALO_GT4 	0x193B
-#define PCI_CHIP_SKYLAKE_SRV_GT2	0x191A
-#define PCI_CHIP_SKYLAKE_SRV_GT3	0x192A
-#define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
-#define PCI_CHIP_SKYLAKE_SRV_GT4	0x193A
-#define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
-#define PCI_CHIP_SKYLAKE_WKS_GT4 	0x193D
-
-#define PCI_CHIP_KABYLAKE_ULT_GT2      0x5916
-#define PCI_CHIP_KABYLAKE_ULT_GT1_5    0x5913
-#define PCI_CHIP_KABYLAKE_ULT_GT1      0x5906
-#define PCI_CHIP_KABYLAKE_ULT_GT3_0    0x5923
-#define PCI_CHIP_KABYLAKE_ULT_GT3_1    0x5926
-#define PCI_CHIP_KABYLAKE_ULT_GT3_2    0x5927
-#define PCI_CHIP_KABYLAKE_ULT_GT2F     0x5921
-#define PCI_CHIP_KABYLAKE_ULX_GT1_5    0x5915
-#define PCI_CHIP_KABYLAKE_ULX_GT1      0x590E
-#define PCI_CHIP_KABYLAKE_ULX_GT2      0x591E
-#define PCI_CHIP_KABYLAKE_DT_GT2       0x5912
-#define PCI_CHIP_KABYLAKE_DT_GT1_5     0x5917
-#define PCI_CHIP_KABYLAKE_DT_GT1       0x5902
-#define PCI_CHIP_KABYLAKE_HALO_GT2     0x591B
-#define PCI_CHIP_KABYLAKE_HALO_GT1_0   0x5908
-#define PCI_CHIP_KABYLAKE_HALO_GT1_1   0x590B
-#define PCI_CHIP_KABYLAKE_HALO_GT4     0x593B
-#define PCI_CHIP_KABYLAKE_SRV_GT2      0x591A
-#define PCI_CHIP_KABYLAKE_SRV_GT1      0x590A
-#define PCI_CHIP_KABYLAKE_WKS_GT2      0x591D
-
-#define PCI_CHIP_BROXTON_0		0x0A84
-#define PCI_CHIP_BROXTON_1		0x1A84
-#define PCI_CHIP_BROXTON_2		0x5A84
-#define PCI_CHIP_BROXTON_3		0x1A85
-#define PCI_CHIP_BROXTON_4		0x5A85
-
 #endif /* __GTK_DOC_IGNORE__ */
 
 #define IS_915G(devid)		(intel_device_info(devid)->is_grantsdale)