diff options
| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2015-10-05 15:48:22 -0700 |
|---|---|---|
| committer | Thomas Wood <thomas.wood@intel.com> | 2015-10-14 15:45:23 +0100 |
| commit | 5bc210a5b5d060a4053d3ad9266123abefb4840a (patch) | |
| tree | 54f217902a5ffc02fb33a483b4cc0225931daa0c /lib/intel_chipset.h | |
| parent | 3e9726b33736f7fd7a349785ab6693e33647240a (diff) | |
lib/kbl: Add Kabylake PCI IDs
Also, following kernel definition Kabylake is Skylake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Diffstat (limited to 'lib/intel_chipset.h')
| -rw-r--r-- | lib/intel_chipset.h | 47 |
1 files changed, 46 insertions, 1 deletions
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 7f611ed1..6fcc2449 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -206,6 +206,25 @@ void intel_check_pch(void); #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A #define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D +#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 +#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913 +#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 +#define PCI_CHIP_KABYLAKE_ULT_GT3 0x5926 +#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 +#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 +#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E +#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E +#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 +#define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 +#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 +#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B +#define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B +#define PCI_CHIP_KABYLAKE_HALO_GT1 0x590B +#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A +#define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A +#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A +#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D + #define PCI_CHIP_BROXTON_0 0x0A84 #define PCI_CHIP_BROXTON_1 0x1A84 #define PCI_CHIP_BROXTON_2 0x5A84 @@ -390,7 +409,33 @@ void intel_check_pch(void); (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ (devid) == PCI_CHIP_SKYLAKE_SRV_GT3) -#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ +#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5|| \ + (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5|| \ + (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5|| \ + (devid) == PCI_CHIP_KABYLAKE_ULT_GT1|| \ + (devid) == PCI_CHIP_KABYLAKE_ULX_GT1|| \ + (devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \ + (devid) == PCI_CHIP_KABYLAKE_HALO_GT1|| \ + (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) + +#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2|| \ + (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F|| \ + (devid) == PCI_CHIP_KABYLAKE_ULX_GT2|| \ + (devid) == PCI_CHIP_KABYLAKE_DT_GT2|| \ + (devid) == PCI_CHIP_KABYLAKE_HALO_GT2|| \ + (devid) == PCI_CHIP_KABYLAKE_SRV_GT2|| \ + (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) + +#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3|| \ + (devid) == PCI_CHIP_KABYLAKE_HALO_GT3|| \ + (devid) == PCI_CHIP_KABYLAKE_SRV_GT3) + +#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ + IS_KBL_GT2(devid) || \ + IS_KBL_GT3(devid)) + +#define IS_SKYLAKE(devid) (IS_KABYLAKE(devid) || \ + IS_SKL_GT1(devid) || \ IS_SKL_GT2(devid) || \ IS_SKL_GT3(devid)) |