diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2011-09-09 20:44:27 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2011-09-12 09:39:16 +0200 |
| commit | 61b9806f4e7b92031491f2c4b3454c1f3afe418c (patch) | |
| tree | 1796c2baecf0eb19bb4517ec0efdc32b4fda14bb /lib/intel_chipset.h | |
| parent | 32f49c7c0d91318c1993e381855ecf4bb02abc80 (diff) | |
tests: basic ring<->cpu and ring<->ring tests
Using a dummy reloc that doesn't matter to trick the kernel into
synchroizing the rings.
v2: properly apply MI_NOOP workaround to MI_FLUSH_DW and
switch to MI_COND_BATCH_BUFFER_END as a dummy command on the
render ring to avoid PIPE_CONTROL errata.
v3: somebody clever decided that in C, you cound from 1,
i.e. I915_EXEC_RENDER == 1. It works now ...
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'lib/intel_chipset.h')
| -rwxr-xr-x | lib/intel_chipset.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index a38f661d..35edaf77 100755 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -169,6 +169,10 @@ #define HAS_BLT_RING(devid) (IS_GEN6(devid) || \ IS_GEN7(devid)) +#define HAS_BSD_RING(devid) (IS_GEN5(devid) || \ + IS_GEN6(devid) || \ + IS_GEN7(devid)) + #define IS_BROADWATER(devid) (devid == PCI_CHIP_I946_GZ || \ devid == PCI_CHIP_I965_G_1 || \ devid == PCI_CHIP_I965_Q || \ |