diff options
| author | Vijay Purushothaman <vijay.a.purushothaman@intel.com> | 2012-08-17 18:06:52 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-08-21 09:30:29 +0200 |
| commit | 4fc76adf313f2792b7438f9372321ce3ea66c6c2 (patch) | |
| tree | f9645fa65a9ef761caa34a33044400282eeac776 /lib/intel_reg.h | |
| parent | 082826de6c66ff76c444434cd56aaf6df80027b3 (diff) | |
tools: Added intel_dpio_read and intel_dpio_write
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'lib/intel_reg.h')
| -rw-r--r-- | lib/intel_reg.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/intel_reg.h b/lib/intel_reg.h index a371d67b..ffded64e 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -3741,5 +3741,18 @@ typedef enum { #define SFUSE_STRAP_DDIC_DETECTED (1<<1) #define SFUSE_STRAP_DDID_DETECTED (1<<0) +/* Valleyview related items */ + +/* Valleyview DPIO registers */ +#define VLV_DISPLAY_BASE 0x180000 +#define DPIO_PKT 0x2100 +#define DPIO_RID (0 << 24) +#define DPIO_OP_WRITE (1 << 16) +#define DPIO_OP_READ (0 << 16) +#define DPIO_PORTID (0x12 << 8) +#define DPIO_BYTE (0xf << 4) +#define DPIO_BUSY (1 << 0) +#define DPIO_DATA 0x2104 +#define DPIO_REG 0x2108 #endif /* _I810_REG_H */ |