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authorBen Widawsky <benjamin.widawsky@intel.com>2013-12-05 14:14:35 -0800
committerBen Widawsky <benjamin.widawsky@intel.com>2013-12-05 14:30:14 -0800
commit672911d7149735ee51cbcff5540b8dcb8a2de321 (patch)
treeea66c0f34fcf8136069d452d8e922ee9751feef3 /lib/intel_reg.h
parent40b586188c021db58a37ef23ac7d3e20547461a1 (diff)
gem_pipe_control_store_loop: BDW update
I've opted to not use the PIPE_CONTROL w/a for now. I am unclear if it is actually required (the test does pass). Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Diffstat (limited to 'lib/intel_reg.h')
-rw-r--r--lib/intel_reg.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 4c1dbd83..f7147e0b 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2709,7 +2709,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define COLOR_BLT_WRITE_ALPHA (1<<21)
#define COLOR_BLT_WRITE_RGB (1<<20)
-#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|(0x4))
+#define XY_COLOR_BLT_CMD_NOLEN ((2<<29)|(0x50<<22))
+#define XY_COLOR_BLT_CMD (XY_COLOR_BLT_CMD_NOLEN|(0x4))
#define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
#define XY_COLOR_BLT_WRITE_RGB (1<<20)
#define XY_COLOR_BLT_TILED (1<<11)