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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-12-03 16:44:08 -0200 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-12-06 13:10:36 -0200 |
| commit | d5cdee95d5e8290adea2757230a7c10728bcd49a (patch) | |
| tree | f43852acfb91448960d01984e3560160e5f16a63 /lib/intel_reg.h | |
| parent | 3906a50ede5fa8d6edfca8bf81809fd0cf229a30 (diff) | |
lib: rename some power well bit names
I did the same change in the Kernel a few months ago. This should help
not getting confused about which bit does what.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Diffstat (limited to 'lib/intel_reg.h')
| -rw-r--r-- | lib/intel_reg.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/intel_reg.h b/lib/intel_reg.h index 1c16e92d..d8eec655 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -3627,8 +3627,8 @@ typedef enum { #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ -#define HSW_PWR_WELL_ENABLE (1<<31) -#define HSW_PWR_WELL_STATE (1<<30) +#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) +#define HSW_PWR_WELL_STATE_ENABLED (1<<30) #define HSW_PWR_WELL_CTL5 0x45410 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) |