diff options
author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-04-18 21:33:42 +0300 |
---|---|---|
committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-04-29 14:56:10 +0300 |
commit | b3fe990dd7ef25fa8f8e47b04fb7522942c6668d (patch) | |
tree | 1d5d80322c098e7948cbc63fc76f4bc0e87fbf9c /lib/rendercopy_gen6.c | |
parent | 6e6f7c00fd860cc61e28e47286118e590f2a4563 (diff) |
lib/rendercopy: Configure MOCS more consistently
Unify the MOCS to be more consistently across the platforms.
Currently gen8+ are specifyig UC whereas earlier platforms
generally use PTE. Let's make everyone more or less specify
L3+PTE.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'lib/rendercopy_gen6.c')
-rw-r--r-- | lib/rendercopy_gen6.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c index b90466d0..83c7d694 100644 --- a/lib/rendercopy_gen6.c +++ b/lib/rendercopy_gen6.c @@ -117,6 +117,8 @@ gen6_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE; ss->ss3.tile_walk = buf->tiling == I915_TILING_Y; + ss->ss5.memory_object_control = GEN6_MOCS_PTE; + return intel_batchbuffer_subdata_offset(batch, ss); } |