diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2018-03-14 18:48:57 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2018-07-06 15:58:56 +0300 |
| commit | ae539ba6553144d9345672ddc991c17563d850b7 (patch) | |
| tree | 3e77d4a17cabbf6050db60466bffb0503f60a5b4 /lib/rendercopy_gen8.c | |
| parent | 78071c2fa53db2f04b8eddc6e6118be4fbc5c2fe (diff) | |
lib/rendercopy: Set the upper 32bits of surface base address on gen8+
gen8 introduces 48 bit virtual addresses. Set both dwords correctly
as otherwise the presumed_offset will not match what we actually
have stored in the surface state if the buffer is located somewhere
above 4GiB.
I guess we're not currently using 48bit addresses with rendercopy?
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'lib/rendercopy_gen8.c')
| -rw-r--r-- | lib/rendercopy_gen8.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c index 4406a0a0..5a9bf32e 100644 --- a/lib/rendercopy_gen8.c +++ b/lib/rendercopy_gen8.c @@ -172,7 +172,8 @@ gen8_bind_buf(struct intel_batchbuffer *batch, else if (buf->tiling == I915_TILING_Y) ss->ss0.tiled_mode = 3; - ss->ss8.base_addr = buf->bo->offset; + ss->ss8.base_addr = buf->bo->offset64; + ss->ss9.base_addr_hi = buf->bo->offset64 >> 32; ret = drm_intel_bo_emit_reloc(batch->bo, intel_batchbuffer_subdata_offset(batch, &ss->ss8), |