diff options
author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-04-18 21:33:42 +0300 |
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committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-04-29 14:56:10 +0300 |
commit | b3fe990dd7ef25fa8f8e47b04fb7522942c6668d (patch) | |
tree | 1d5d80322c098e7948cbc63fc76f4bc0e87fbf9c /lib/rendercopy_gen8.c | |
parent | 6e6f7c00fd860cc61e28e47286118e590f2a4563 (diff) |
lib/rendercopy: Configure MOCS more consistently
Unify the MOCS to be more consistently across the platforms.
Currently gen8+ are specifyig UC whereas earlier platforms
generally use PTE. Let's make everyone more or less specify
L3+PTE.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'lib/rendercopy_gen8.c')
-rw-r--r-- | lib/rendercopy_gen8.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c index f7a33947..e22d8501 100644 --- a/lib/rendercopy_gen8.c +++ b/lib/rendercopy_gen8.c @@ -16,6 +16,7 @@ #include "drmtest.h" #include "intel_bufmgr.h" #include "intel_batchbuffer.h" +#include "intel_chipset.h" #include "intel_io.h" #include "rendercopy.h" #include "gen8_render.h" @@ -181,6 +182,12 @@ gen8_bind_buf(struct intel_batchbuffer *batch, else if (buf->tiling == I915_TILING_Y) ss->ss0.tiled_mode = 3; + if (IS_CHERRYVIEW(batch->devid)) + ss->ss1.memory_object_control = CHV_MOCS_WB | CHV_MOCS_L3; + else + ss->ss1.memory_object_control = BDW_MOCS_PTE | + BDW_MOCS_TC_L3_PTE | BDW_MOCS_AGE(0); + ss->ss8.base_addr = buf->bo->offset64; ss->ss9.base_addr_hi = buf->bo->offset64 >> 32; |