diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2018-03-14 18:54:05 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2018-07-06 16:00:47 +0300 |
| commit | 6cc21d7caded2800810a4e11d4c00aaa1cf47aa4 (patch) | |
| tree | 4ef203801c8d30c9efd9f1b3c4da5bd3155de16d /lib/rendercopy_gen9.c | |
| parent | a4393c3951ec6eb20901b4883c6549ea36affc33 (diff) | |
lib/rendercopy: Add enough surface state for AUX_CCS_E
Populate the gen8+ SURFACE_STATE aux bits correctly.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'lib/rendercopy_gen9.c')
| -rw-r--r-- | lib/rendercopy_gen9.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index db59c9f4..d9e7eaf9 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -189,6 +189,20 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, ss->ss7.shader_chanel_select_b = 6; ss->ss7.shader_chanel_select_a = 7; + if (buf->aux.stride) { + ss->ss6.aux_mode = 0x5; /* AUX_CCS_E */ + ss->ss6.aux_pitch = (buf->aux.stride / 128) - 1; + + ss->ss10.aux_base_addr = buf->bo->offset64 + buf->aux.offset; + ss->ss11.aux_base_addr_hi = (buf->bo->offset64 + buf->aux.offset) >> 32; + + ret = drm_intel_bo_emit_reloc(batch->bo, + intel_batchbuffer_subdata_offset(batch, &ss->ss10), + buf->bo, buf->aux.offset, + read_domain, write_domain); + assert(ret == 0); + } + return offset; } |