diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-03-04 17:47:37 -0800 |
|---|---|---|
| committer | Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> | 2019-03-11 15:06:12 -0700 |
| commit | 7a9e536e5c6488fa58998506eeda44794ea3cdc6 (patch) | |
| tree | 2463c6d5596c25c6ae26e7635df5214778efdde2 /lib/rendercopy_gen9.c | |
| parent | 7c2fdd9b8d281659a9aa1c64d80280973fef5d4d (diff) | |
lib/rendercopy: Add support for Yf/Ys tiling to gen9 rendercopy
Set up the surface state accordingly to support Yf/Ys tiling.
>From DK:
Rebase.
Move support to gen-9 surface state
Cc: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
Diffstat (limited to 'lib/rendercopy_gen9.c')
| -rw-r--r-- | lib/rendercopy_gen9.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index b21b43c0..2cf1ab16 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -204,9 +204,15 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf, ss->ss0.horizontal_alignment = 1; /* align 4 */ if (buf->tiling == I915_TILING_X) ss->ss0.tiled_mode = 2; - else if (buf->tiling == I915_TILING_Y) + else if (buf->tiling != I915_TILING_NONE) ss->ss0.tiled_mode = 3; + if (buf->tiling == I915_TILING_Yf) + ss->ss5.trmode = 1; + else if (buf->tiling == I915_TILING_Ys) + ss->ss5.trmode = 2; + ss->ss5.mip_tail_start_lod = 1; /* needed with trmode */ + ss->ss8.base_addr = buf->bo->offset64; ss->ss9.base_addr_hi = buf->bo->offset64 >> 32; |