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authorZhao Yakui <yakui.zhao@intel.com>2014-01-22 09:37:25 +0800
committerDamien Lespiau <damien.lespiau@intel.com>2014-09-30 12:21:03 +0100
commit8e62f78999281ad4bc7b9981b127830d0d3796d9 (patch)
treed1efd0e0cc41e20a4f27940b5258ab9c42a0f199 /lib/rendercopy_gen9.c
parent833e47662436094646f8510e7f9e7b3edd3d6b89 (diff)
rendercopy/skl: Emit 3DSTATE_WM_HZ_OP
This is from that on BDW. Without it, the pixel pipeline can't work well. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Diffstat (limited to 'lib/rendercopy_gen9.c')
-rw-r--r--lib/rendercopy_gen9.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 1aacaa21..52fc90f6 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -715,8 +715,19 @@ gen9_emit_ds(struct intel_batchbuffer *batch) {
OUT_BATCH(0);
}
+
+static void
+gen8_emit_wm_hz_op(struct intel_batchbuffer *batch) {
+ OUT_BATCH(GEN8_3DSTATE_WM_HZ_OP | (5-2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
static void
gen8_emit_null_state(struct intel_batchbuffer *batch) {
+ gen8_emit_wm_hz_op(batch);
gen8_emit_hs(batch);
OUT_BATCH(GEN7_3DSTATE_TE | (4-2));
OUT_BATCH(0);