lib/rendercopy: Assert that buffer dimensions/stride are acceptable

Sprinkle some asserts into rendercopy to make sure we don't try
to exceed the render engine surface size/stride limitations.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

7 files changed, 37 insertions, 0 deletions

diff --git a/lib/rendercopy_gen4.c b/lib/rendercopy_gen4.c
index 67460c04..9111508f 100644
--- a/lib/rendercopy_gen4.c
+++ b/lib/rendercopy_gen4.c
@@ -142,6 +142,10 @@ gen4_bind_buf(struct intel_batchbuffer *batch,
 	uint32_t write_domain, read_domain;
 	int ret;
 
+	igt_assert_lte(buf->stride, 128*1024);
+	igt_assert_lte(igt_buf_width(buf), 8192);
+	igt_assert_lte(igt_buf_height(buf), 8192);
+
 	if (is_dst) {
 		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
 	} else {
diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c
index f4c0105a..a6157cfc 100644
--- a/lib/rendercopy_gen6.c
+++ b/lib/rendercopy_gen6.c
@@ -79,6 +79,10 @@ gen6_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf,
 	uint32_t write_domain, read_domain;
 	int ret;
 
+	igt_assert_lte(buf->stride, 128*1024);
+	igt_assert_lte(igt_buf_width(buf), 8192);
+	igt_assert_lte(igt_buf_height(buf), 8192);
+
 	if (is_dst) {
 		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
 	} else {
diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c
index a790217c..0a5d4a15 100644
--- a/lib/rendercopy_gen7.c
+++ b/lib/rendercopy_gen7.c
@@ -65,6 +65,10 @@ gen7_bind_buf(struct intel_batchbuffer *batch,
 	uint32_t write_domain, read_domain;
 	int ret;
 
+	igt_assert_lte(buf->stride, 256*1024);
+	igt_assert_lte(igt_buf_width(buf), 16384);
+	igt_assert_lte(igt_buf_height(buf), 16384);
+
 	switch (buf->bpp) {
 		case 8: format = SURFACEFORMAT_R8_UNORM; break;
 		case 16: format = SURFACEFORMAT_R8G8_UNORM; break;
diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c
index 1c61b00c..643b6630 100644
--- a/lib/rendercopy_gen8.c
+++ b/lib/rendercopy_gen8.c
@@ -150,6 +150,10 @@ gen8_bind_buf(struct intel_batchbuffer *batch,
 	uint32_t write_domain, read_domain, offset;
 	int ret;
 
+	igt_assert_lte(buf->stride, 256*1024);
+	igt_assert_lte(igt_buf_width(buf), 16384);
+	igt_assert_lte(igt_buf_height(buf), 16384);
+
 	if (is_dst) {
 		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
 	} else {
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 2cf1ab16..93e9d150 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -180,6 +180,10 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf,
 	uint32_t write_domain, read_domain, offset;
 	int ret;
 
+	igt_assert_lte(buf->stride, 256*1024);
+	igt_assert_lte(igt_buf_width(buf), 16384);
+	igt_assert_lte(igt_buf_height(buf), 16384);
+
 	if (is_dst) {
 		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
 	} else {
diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c
index c19a6a38..e8c04718 100644
--- a/lib/rendercopy_i830.c
+++ b/lib/rendercopy_i830.c
@@ -138,6 +138,10 @@ static void gen2_emit_target(struct intel_batchbuffer *batch,
 	uint32_t tiling;
 	uint32_t format;
 
+	igt_assert_lte(dst->stride, 8192);
+	igt_assert_lte(igt_buf_width(dst), 2048);
+	igt_assert_lte(igt_buf_height(dst), 2048);
+
 	switch (dst->bpp) {
 		case 8: format = COLR_BUF_8BIT; break;
 		case 16: format = COLR_BUF_RGB565; break;
@@ -175,6 +179,10 @@ static void gen2_emit_texture(struct intel_batchbuffer *batch,
 	uint32_t tiling;
 	uint32_t format;
 
+	igt_assert_lte(src->stride, 8192);
+	igt_assert_lte(igt_buf_width(src), 2048);
+	igt_assert_lte(igt_buf_height(src), 2048);
+
 	switch (src->bpp) {
 		case 8: format = MAPSURF_8BIT | MT_8BIT_L8; break;
 		case 16: format = MAPSURF_16BIT | MT_16BIT_RGB565; break;
diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c
index b28fa98d..1baa7a1b 100644
--- a/lib/rendercopy_i915.c
+++ b/lib/rendercopy_i915.c
@@ -87,6 +87,11 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch,
 	{
 #define TEX_COUNT 1
 		uint32_t format_bits, tiling_bits = 0;
+
+		igt_assert_lte(src->stride, 8192);
+		igt_assert_lte(igt_buf_width(src), 2048);
+		igt_assert_lte(igt_buf_height(src), 2048);
+
 		if (src->tiling != I915_TILING_NONE)
 			tiling_bits = MS3_TILED_SURFACE;
 		if (src->tiling == I915_TILING_Y)
@@ -123,6 +128,10 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch,
 		uint32_t tiling_bits = 0;
 		uint32_t format_bits;
 
+		igt_assert_lte(dst->stride, 8192);
+		igt_assert_lte(igt_buf_width(dst), 2048);
+		igt_assert_lte(igt_buf_height(dst), 2048);
+
 		switch (dst->bpp) {
 			case 8: format_bits = COLR_BUF_8BIT; break;
 			case 16: format_bits = COLR_BUF_RGB565; break;