lib: Start weaning off defunct intel_chipset.h

Several years ago we made the plan of only having one canonical source
for i915_pciids.h, the kernel and everyone importing their definitions
from that. For consistency, we style the intel_device_info after the
kernel, most notably using a generation mask and a per-codename bitfield.

This first step converts looking up the generation for a devid tree from
a massive if(devid)-chain to a (cached) table lookup.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

6 files changed, 472 insertions, 100 deletions

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 3589e26a..8cad9d57 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -26,11 +26,12 @@ libintel_tools_la_SOURCES = 	\
 	instdone.h		\
 	intel_batchbuffer.c	\
 	intel_batchbuffer.h	\
+	intel_chipset.c		\
 	intel_chipset.h		\
+	intel_device_info.c	\
 	intel_os.c		\
 	intel_io.h		\
 	intel_mmio.c		\
-	intel_chipset.c		\
 	intel_reg.h		\
 	ioctl_wrappers.c	\
 	ioctl_wrappers.h	\
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 884fe7cc..62dd042c 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -127,7 +127,7 @@ static bool has_known_intel_chipset(int fd)
 	if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)))
 		return false;
 
-	if (!IS_INTEL(devid))
+	if (!intel_gen(devid))
 		return false;
 
 	__drm_device_id = devid;
diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
index 8a10f5c3..33466bfc 100644
--- a/lib/i915_pciids.h
+++ b/lib/i915_pciids.h
@@ -191,8 +191,8 @@
 	INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
 	INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
-	INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
-	INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
+	INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
+	INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
 	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
@@ -208,4 +208,132 @@
 #define INTEL_VLV_D_IDS(info) \
 	INTEL_VGA_DEVICE(0x0155, info)
 
+#define INTEL_BDW_GT12M_IDS(info)  \
+	INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
+	INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
+	INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
+	INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
+	INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
+	INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
+	INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
+	INTEL_VGA_DEVICE(0x161E, info)  /* GT2 ULX */
+
+#define INTEL_BDW_GT12D_IDS(info) \
+	INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
+	INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
+	INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
+	INTEL_VGA_DEVICE(0x161D, info)  /* GT2 Workstation */
+
+#define INTEL_BDW_GT3M_IDS(info) \
+	INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
+	INTEL_VGA_DEVICE(0x162E, info)  /* ULX */
+
+#define INTEL_BDW_GT3D_IDS(info) \
+	INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
+	INTEL_VGA_DEVICE(0x162D, info)  /* Workstation */
+
+#define INTEL_BDW_RSVDM_IDS(info) \
+	INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
+	INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
+	INTEL_VGA_DEVICE(0x163E, info)  /* ULX */
+
+#define INTEL_BDW_RSVDD_IDS(info) \
+	INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
+	INTEL_VGA_DEVICE(0x163D, info)  /* Workstation */
+
+#define INTEL_BDW_M_IDS(info) \
+	INTEL_BDW_GT12M_IDS(info), \
+	INTEL_BDW_GT3M_IDS(info), \
+	INTEL_BDW_RSVDM_IDS(info)
+
+#define INTEL_BDW_D_IDS(info) \
+	INTEL_BDW_GT12D_IDS(info), \
+	INTEL_BDW_GT3D_IDS(info), \
+	INTEL_BDW_RSVDD_IDS(info)
+
+#define INTEL_CHV_IDS(info) \
+	INTEL_VGA_DEVICE(0x22b0, info), \
+	INTEL_VGA_DEVICE(0x22b1, info), \
+	INTEL_VGA_DEVICE(0x22b2, info), \
+	INTEL_VGA_DEVICE(0x22b3, info)
+
+#define INTEL_SKL_GT1_IDS(info)	\
+	INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
+	INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+	INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
+	INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
+	INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
+
+#define INTEL_SKL_GT2_IDS(info)	\
+	INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
+	INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
+	INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
+	INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
+	INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
+	INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
+
+#define INTEL_SKL_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
+	INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
+	INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
+	INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
+	INTEL_VGA_DEVICE(0x192A, info)  /* SRV GT3 */
+
+#define INTEL_SKL_GT4_IDS(info) \
+	INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
+	INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
+	INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
+	INTEL_VGA_DEVICE(0x193A, info)  /* SRV GT4 */
+
+#define INTEL_SKL_IDS(info)	 \
+	INTEL_SKL_GT1_IDS(info), \
+	INTEL_SKL_GT2_IDS(info), \
+	INTEL_SKL_GT3_IDS(info), \
+	INTEL_SKL_GT4_IDS(info)
+
+#define INTEL_BXT_IDS(info) \
+	INTEL_VGA_DEVICE(0x0A84, info), \
+	INTEL_VGA_DEVICE(0x1A84, info), \
+	INTEL_VGA_DEVICE(0x1A85, info), \
+	INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
+	INTEL_VGA_DEVICE(0x5A85, info)  /* APL HD Graphics 500 */
+
+#define INTEL_KBL_GT1_IDS(info)	\
+	INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
+	INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
+	INTEL_VGA_DEVICE(0x5917, info), /* DT  GT1.5 */ \
+	INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+	INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+	INTEL_VGA_DEVICE(0x5902, info), /* DT  GT1 */ \
+	INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
+	INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
+	INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
+
+#define INTEL_KBL_GT2_IDS(info)	\
+	INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+	INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
+	INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
+	INTEL_VGA_DEVICE(0x5912, info), /* DT  GT2 */ \
+	INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
+	INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
+	INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
+
+#define INTEL_KBL_GT3_IDS(info) \
+	INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
+	INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
+	INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
+
+#define INTEL_KBL_GT4_IDS(info) \
+	INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
+
+#define INTEL_KBL_IDS(info) \
+	INTEL_KBL_GT1_IDS(info), \
+	INTEL_KBL_GT2_IDS(info), \
+	INTEL_KBL_GT3_IDS(info), \
+	INTEL_KBL_GT4_IDS(info)
+
 #endif /* _I915_PCIIDS_H */
diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
index 56746b00..777dfa73 100644
--- a/lib/intel_chipset.c
+++ b/lib/intel_chipset.c
@@ -141,37 +141,6 @@ intel_get_drm_devid(int fd)
 }
 
 /**
- * intel_gen:
- * @devid: pci device id
- *
- * Computes the Intel GFX generation for the give device id.
- *
- * Returns:
- * The GFX generation on successful lookup, -1 on failure.
- */
-int intel_gen(uint32_t devid)
-{
-	if (IS_GEN2(devid))
-		return 2;
-	if (IS_GEN3(devid))
-		return 3;
-	if (IS_GEN4(devid))
-		return 4;
-	if (IS_GEN5(devid))
-		return 5;
-	if (IS_GEN6(devid))
-		return 6;
-	if (IS_GEN7(devid))
-		return 7;
-	if (IS_GEN8(devid))
-		return 8;
-	if (IS_GEN9(devid))
-		return 9;
-
-	return -1;
-}
-
-/**
  * intel_check_pch:
  *
  * Detects the PCH chipset type of the running systems and fills in the results
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index e1e552c0..69c878bd 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -29,10 +29,44 @@
 #define _INTEL_CHIPSET_H
 
 #include <pciaccess.h>
+#include <stdbool.h>
 
 struct pci_device *intel_get_pci_device(void);
 uint32_t intel_get_drm_devid(int fd);
-int intel_gen(uint32_t devid);
+
+const struct intel_device_info {
+	unsigned gen;
+	bool is_mobile : 1;
+	bool is_whitney : 1;
+	bool is_almador : 1;
+	bool is_brookdale : 1;
+	bool is_montara : 1;
+	bool is_springdale : 1;
+	bool is_grantsdale : 1;
+	bool is_alviso : 1;
+	bool is_lakeport : 1;
+	bool is_calistoga : 1;
+	bool is_bearlake : 1;
+	bool is_pineview : 1;
+	bool is_broadwater : 1;
+	bool is_crestline : 1;
+	bool is_eaglelake : 1;
+	bool is_cantiga : 1;
+	bool is_ironlake : 1;
+	bool is_arrandale : 1;
+	bool is_sandybridge : 1;
+	bool is_ivybridge : 1;
+	bool is_valleyview : 1;
+	bool is_haswell : 1;
+	bool is_broadwell : 1;
+	bool is_cherryview : 1;
+	bool is_skylake : 1;
+	bool is_broxton : 1;
+	bool is_kabylake : 1;
+	const char *codename;
+} *intel_device_info(uint16_t devid) __attribute__((pure));
+
+unsigned intel_gen(uint16_t devid) __attribute__((pure));
 
 extern enum pch_type intel_pch;
 
@@ -275,36 +309,6 @@ void intel_check_pch(void);
 				 (devid) == PCI_CHIP_Q33_G || \
 				 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
 
-#define IS_GEN2(devid)		((devid) == PCI_CHIP_I830_M || \
-				 (devid) == PCI_CHIP_845_G || \
-				 (devid) == PCI_CHIP_I854_G || \
-				 (devid) == PCI_CHIP_I855_GM || \
-				 (devid) == PCI_CHIP_I865_G)
-
-#define IS_GEN3(devid)		(IS_945(devid) || IS_915(devid))
-
-#define IS_GEN4(devid)		((devid) == PCI_CHIP_I965_G || \
-				 (devid) == PCI_CHIP_I965_Q || \
-				 (devid) == PCI_CHIP_I965_G_1 || \
-				 (devid) == PCI_CHIP_I965_GM || \
-				 (devid) == PCI_CHIP_I965_GME || \
-				 (devid) == PCI_CHIP_I946_GZ || \
-				 IS_G4X(devid))
-
-#define IS_GEN5(devid)		(IS_ILD(devid) || IS_ILM(devid))
-
-#define IS_GEN6(devid)		((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
-				 (devid) == PCI_CHIP_SANDYBRIDGE_S)
-
-#define IS_GEN7(devid)		(IS_IVYBRIDGE(devid) || \
-				 IS_HASWELL(devid) || \
-				 IS_VALLEYVIEW(devid))
-
 #define IS_IVYBRIDGE(devid)	((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
 				 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
 				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
@@ -396,9 +400,6 @@ void intel_check_pch(void);
 				 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
 				 (devid) == PCI_CHIP_CHERRYVIEW_3)
 
-#define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
-				 IS_CHERRYVIEW(devid))
-
 #define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
 				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1	|| \
 				 (devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
@@ -462,10 +463,6 @@ void intel_check_pch(void);
 				 (devid) == PCI_CHIP_BROXTON_3 || \
 				 (devid) == PCI_CHIP_BROXTON_4)
 
-#define IS_GEN9(devid)		(IS_KABYLAKE(devid) || \
-				 IS_SKYLAKE(devid) || \
-				 IS_BROXTON(devid))
-
 #define IS_965(devid)		(IS_GEN4(devid) || \
 				 IS_GEN5(devid) || \
 				 IS_GEN6(devid) || \
@@ -473,32 +470,6 @@ void intel_check_pch(void);
 				 IS_GEN8(devid) || \
 				 IS_GEN9(devid))
 
-#define IS_INTEL(devid)		(IS_GEN2(devid) || \
-				 IS_GEN3(devid) || \
-				 IS_GEN4(devid) || \
-				 IS_GEN5(devid) || \
-				 IS_GEN6(devid) || \
-				 IS_GEN7(devid) || \
-				 IS_GEN8(devid) || \
-				 IS_GEN9(devid))
-
-#define HAS_PCH_SPLIT(devid)	(IS_GEN5(devid) || \
-				 IS_GEN6(devid) || \
-				 IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
-				 IS_BROADWELL(devid) || \
-				 IS_SKYLAKE(devid))
-
-#define HAS_BLT_RING(devid)	(IS_GEN6(devid) || \
-				 IS_GEN7(devid) || \
-				 IS_GEN8(devid) || \
-				 IS_GEN9(devid))
-
-#define HAS_BSD_RING(devid)	(IS_GEN5(devid) || \
-				 IS_GEN6(devid) || \
-				 IS_GEN7(devid) || \
-				 IS_GEN8(devid) || \
-				 IS_GEN9(devid))
-
 #define IS_BROADWATER(devid)	((devid) == PCI_CHIP_I946_GZ || \
 				 (devid) == PCI_CHIP_I965_G_1 || \
 				 (devid) == PCI_CHIP_I965_Q || \
@@ -507,6 +478,21 @@ void intel_check_pch(void);
 #define IS_CRESTLINE(devid)	((devid) == PCI_CHIP_I965_GM || \
 				 (devid) == PCI_CHIP_I965_GME)
 
-#define HAS_VEBOX_RING(devid)   (IS_HASWELL(devid))
+#define IS_GEN(devid, x)	(intel_device_info(devid)->gen & (1u << ((x)-1)))
+#define AT_LEAST_GEN(devid, x)	(intel_device_info(devid)->gen & -(1u << ((x)-1)))
+
+#define IS_GEN2(devid)		IS_GEN(devid, 2)
+#define IS_GEN3(devid)		IS_GEN(devid, 3)
+#define IS_GEN4(devid)		IS_GEN(devid, 4)
+#define IS_GEN5(devid)		IS_GEN(devid, 5)
+#define IS_GEN6(devid)		IS_GEN(devid, 6)
+#define IS_GEN7(devid)		IS_GEN(devid, 7)
+#define IS_GEN8(devid)		IS_GEN(devid, 8)
+#define IS_GEN9(devid)		IS_GEN(devid, 9)
+
+#define HAS_BSD_RING(devid)	AT_LEAST_GEN(devid, 5)
+#define HAS_BLT_RING(devid)	AT_LEAST_GEN(devid, 6)
+
+#define HAS_PCH_SPLIT(devid)	AT_LEAST_GEN(devid, 5) /* XXX Valleyview? */
 
 #endif /* _INTEL_CHIPSET_H */
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
new file mode 100644
index 00000000..9e194945
--- /dev/null
+++ b/lib/intel_device_info.c
@@ -0,0 +1,288 @@
+#include "intel_chipset.h"
+#include "i915_pciids.h"
+
+#include <strings.h> /* ffs() */
+
+#define BIT(x) (1<<(x))
+
+static const struct intel_device_info intel_generic_info = {
+	.gen = 0,
+};
+
+static const struct intel_device_info intel_i81x_info = {
+	.gen = BIT(0),
+	.is_whitney = true,
+	.codename = "solano" /* 815 == "whitney" ? or vice versa? */
+};
+
+static const struct intel_device_info intel_i830_info = {
+	.gen = BIT(1),
+	.is_almador = true,
+	.codename = "almador"
+};
+static const struct intel_device_info intel_i845_info = {
+	.gen = BIT(1),
+	.is_brookdale = true,
+	.codename = "brookdale"
+};
+static const struct intel_device_info intel_i855_info = {
+	.gen = BIT(1),
+	.is_mobile = true,
+	.is_montara = true,
+	.codename = "montara"
+};
+static const struct intel_device_info intel_i865_info = {
+	.gen = BIT(1),
+	.is_springdale = true,
+	.codename = "spingdale"
+};
+
+static const struct intel_device_info intel_i915_info = {
+	.gen = BIT(2),
+	.is_grantsdale = true,
+	.codename = "grantsdale"
+};
+static const struct intel_device_info intel_i915m_info = {
+	.gen = BIT(2),
+	.is_mobile = true,
+	.is_alviso = true,
+	.codename = "alviso"
+};
+static const struct intel_device_info intel_i945_info = {
+	.gen = BIT(2),
+	.is_lakeport = true,
+	.codename = "lakeport"
+};
+static const struct intel_device_info intel_i945m_info = {
+	.gen = BIT(2),
+	.is_mobile = true,
+	.is_calistoga = true,
+	.codename = "calistoga"
+};
+
+static const struct intel_device_info intel_g33_info = {
+	.gen = BIT(2),
+	.is_bearlake = true,
+	.codename = "bearlake"
+};
+static const struct intel_device_info intel_pineview_info = {
+	.gen = BIT(2),
+	.is_mobile = true,
+	.is_pineview = true,
+	.codename = "pineview"
+};
+
+static const struct intel_device_info intel_i965_info = {
+	.gen = BIT(3),
+	.is_broadwater = true,
+	.codename = "broadwater"
+};
+
+static const struct intel_device_info intel_i965m_info = {
+	.gen = BIT(3),
+	.is_mobile = true,
+	.is_crestline = true,
+	.codename = "crestline"
+};
+
+static const struct intel_device_info intel_g45_info = {
+	.gen = BIT(3),
+	.is_eaglelake = true,
+	.codename = "aaglelake"
+};
+static const struct intel_device_info intel_gm45_info = {
+	.gen = BIT(3),
+	.is_mobile = true,
+	.is_cantiga = true,
+	.codename = "cantiga"
+};
+
+static const struct intel_device_info intel_ironlake_info = {
+	.gen = BIT(4),
+	.is_ironlake = true,
+	.codename = "ironlake"
+};
+static const struct intel_device_info intel_ironlake_m_info = {
+	.gen = BIT(4),
+	.is_mobile = true,
+	.is_arrandale = true,
+	.codename = "arrandale"
+};
+
+static const struct intel_device_info intel_sandybridge_info = {
+	.gen = BIT(5),
+	.is_sandybridge = true,
+	.codename = "sandybridge"
+};
+static const struct intel_device_info intel_sandybridge_m_info = {
+	.gen = BIT(5),
+	.is_mobile = true,
+	.is_sandybridge = true,
+	.codename = "sandybridge"
+};
+
+static const struct intel_device_info intel_ivybridge_info = {
+	.gen = BIT(6),
+	.is_ivybridge = true,
+	.codename = "ivybridge"
+};
+static const struct intel_device_info intel_ivybridge_m_info = {
+	.gen = BIT(6),
+	.is_mobile = true,
+	.is_ivybridge = true,
+	.codename = "ivybridge"
+};
+
+static const struct intel_device_info intel_valleyview_info = {
+	.gen = BIT(6),
+	.is_valleyview = true,
+	.codename = "valleyview"
+};
+static const struct intel_device_info intel_valleyview_m_info = {
+	.gen = BIT(6),
+	.is_mobile = true,
+	.is_valleyview = true,
+	.codename = "valleyview"
+};
+
+static const struct intel_device_info intel_haswell_info = {
+	.gen = BIT(6),
+	.is_haswell = true,
+	.codename = "haswell"
+};
+static const struct intel_device_info intel_haswell_m_info = {
+	.gen = BIT(6),
+	.is_mobile = true,
+	.is_haswell = true,
+	.codename = "haswell"
+};
+
+static const struct intel_device_info intel_broadwell_info = {
+	.gen = BIT(7),
+	.is_broadwell = true,
+	.codename = "broadwell"
+};
+static const struct intel_device_info intel_broadwell_m_info = {
+	.gen = BIT(7),
+	.is_mobile = true,
+	.is_broadwell = true,
+	.codename = "broadwell"
+};
+
+static const struct intel_device_info intel_cherryview_info = {
+	.gen = BIT(7),
+	.is_cherryview = true,
+	.codename = "cherryview"
+};
+
+static const struct intel_device_info intel_skylake_info = {
+	.gen = BIT(8),
+	.is_skylake = true,
+	.codename = "skylake"
+};
+
+static const struct intel_device_info intel_broxton_info = {
+	.gen = BIT(8),
+	.is_broxton = true,
+	.codename = "broxton"
+};
+
+static const struct intel_device_info intel_kabylake_info = {
+	.gen = BIT(8),
+	.is_kabylake = true,
+	.codename = "kabylake"
+};
+
+static const struct pci_id_match intel_device_match[] = {
+	INTEL_I830_IDS(&intel_i830_info),
+	INTEL_I845G_IDS(&intel_i845_info),
+	INTEL_I85X_IDS(&intel_i855_info),
+	INTEL_I865G_IDS(&intel_i865_info),
+
+	INTEL_I915G_IDS(&intel_i915_info),
+	INTEL_I915GM_IDS(&intel_i915m_info),
+	INTEL_I945G_IDS(&intel_i945_info),
+	INTEL_I945GM_IDS(&intel_i945m_info),
+
+	INTEL_G33_IDS(&intel_g33_info),
+	INTEL_PINEVIEW_IDS(&intel_pineview_info),
+
+	INTEL_I965G_IDS(&intel_i965_info),
+	INTEL_I965GM_IDS(&intel_i965m_info),
+
+	INTEL_G45_IDS(&intel_g45_info),
+	INTEL_GM45_IDS(&intel_gm45_info),
+
+	INTEL_IRONLAKE_D_IDS(&intel_ironlake_info),
+	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
+
+	INTEL_SNB_D_IDS(&intel_sandybridge_info),
+	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
+
+	INTEL_IVB_D_IDS(&intel_ivybridge_info),
+	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
+
+	INTEL_HSW_D_IDS(&intel_haswell_info),
+	INTEL_HSW_M_IDS(&intel_haswell_m_info),
+
+	INTEL_VLV_D_IDS(&intel_valleyview_info),
+	INTEL_VLV_M_IDS(&intel_valleyview_m_info),
+
+	INTEL_BDW_D_IDS(&intel_broadwell_info),
+	INTEL_BDW_M_IDS(&intel_broadwell_m_info),
+
+	INTEL_CHV_IDS(&intel_cherryview_info),
+
+	INTEL_SKL_IDS(&intel_skylake_info),
+
+	INTEL_BXT_IDS(&intel_broxton_info),
+
+	INTEL_KBL_IDS(&intel_kabylake_info),
+
+	INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
+};
+
+/**
+ * intel_device_info:
+ * @devid: pci device id
+ *
+ * Looks up the Intel GFX device info for the given device id.
+ *
+ * Returns:
+ * The associated intel_device_info
+ */
+const struct intel_device_info *intel_device_info(uint16_t devid)
+{
+	static const struct intel_device_info *cache = &intel_generic_info;
+	static uint16_t cached_devid;
+	int i;
+
+	if (cached_devid == devid)
+		goto out;
+
+	/* XXX Presort table and bsearch! */
+	for (i = 0; intel_device_match[i].device_id != PCI_MATCH_ANY; i++) {
+		if (devid == intel_device_match[i].device_id)
+			break;
+	}
+
+	cached_devid = devid;
+	cache = (void *)intel_device_match[i].match_data;
+
+out:
+	return cache;
+}
+
+/**
+ * intel_gen:
+ * @devid: pci device id
+ *
+ * Computes the Intel GFX generation for the given device id.
+ *
+ * Returns:
+ * The GFX generation on successful lookup, 0 on failure.
+ */
+unsigned intel_gen(uint16_t devid)
+{
+	return ffs(intel_device_info(devid)->gen);
+}