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| author | Thomas Wood <thomas.wood@intel.com> | 2014-11-28 11:02:44 +0000 |
|---|---|---|
| committer | Thomas Wood <thomas.wood@intel.com> | 2014-12-04 16:07:55 +0000 |
| commit | b2ac2642a9b5448761086bdb8ae1a1e2974b3995 (patch) | |
| tree | 48c6e835a0b62de686a6889847c3176cd77637fe /tests/gem_pipe_control_store_loop.c | |
| parent | 029dee797965357dbcbe5a097731701e4d965d82 (diff) | |
tests: add more test descriptions
Add more test descriptions based on exiting comments.
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Diffstat (limited to 'tests/gem_pipe_control_store_loop.c')
| -rw-r--r-- | tests/gem_pipe_control_store_loop.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/gem_pipe_control_store_loop.c b/tests/gem_pipe_control_store_loop.c index 86681f2a..86ee4050 100644 --- a/tests/gem_pipe_control_store_loop.c +++ b/tests/gem_pipe_control_store_loop.c @@ -47,6 +47,8 @@ #include "intel_chipset.h" #include "intel_io.h" +IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW writes."); + static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; uint32_t devid; |