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authorChris Wilson <chris@chris-wilson.co.uk>2017-01-18 09:53:41 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2017-01-18 18:15:49 +0000
commit74d0912396af0bfab1d2c90f609abc42c3e8990b (patch)
treecdf23d1f809dfa4291ff75d92ba3994a5bac458a /tests/intel-ci
parent10cc01e1eea8f9bd64eeba083869b79d6dab1170 (diff)
intel-ci: Do module reload last
We want to run the initial set of tests under "pristine startup" conditions - so that our tests see the hardware as close to the condition we normally would after booting. This means that we want to avoid reloading the module until the very last set of tests. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Petri Latvala <petri.latvala@intel.com> Acked-by: Petri Latvala <petri.latvala@intel.com>
Diffstat (limited to 'tests/intel-ci')
-rw-r--r--tests/intel-ci/fast-feedback.testlist6
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index 42042f18..a6b56f35 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -3,9 +3,6 @@ igt@core_prop_blob@basic
igt@drv_getparams_basic@basic-eu-total
igt@drv_getparams_basic@basic-subslice-total
igt@drv_hangman@error-state-basic
-igt@drv_module_reload@basic-reload
-igt@drv_module_reload@basic-reload-inject
-igt@drv_module_reload@basic-reload-final
igt@gem_basic@bad-close
igt@gem_basic@create-close
igt@gem_basic@create-fd-close
@@ -244,3 +241,6 @@ igt@vgem_basic@mmap
igt@vgem_basic@second-client
igt@vgem_basic@sysfs
igt@vgem_basic@unload
+igt@drv_module_reload@basic-reload
+igt@drv_module_reload@basic-reload-inject
+igt@drv_module_reload@basic-reload-final