diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2017-10-18 15:13:48 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2017-10-19 07:07:11 +0100 |
| commit | d4a4fbec0c079c7bec7fa6a2c756eea02314799e (patch) | |
| tree | 54b387c3b0041d24815d037c467b59dc86cbb8c8 /tests/prime_mmap_coherency.c | |
| parent | 9a3f6f59d4c208219f7d3178106bdef628ff68d0 (diff) | |
igt/prime_mmap_coherency: Call prime_sync_start before read after write
We never declared that we were about to read from the mmap after copying
into it using the BLT (a missed call to prime_sync_start); leaving its
coherency ill-defined. For completeness, add the missing
prime_sync_end() as well.
v2: Another prime_sync_start/end around the is-zero check in
test_read_flush()
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103168
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tests/prime_mmap_coherency.c')
| -rw-r--r-- | tests/prime_mmap_coherency.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c index a213ac0f..ffd2d751 100644 --- a/tests/prime_mmap_coherency.c +++ b/tests/prime_mmap_coherency.c @@ -80,8 +80,10 @@ static int test_read_flush(void) MAP_SHARED, dma_buf_fd, 0); igt_assert(ptr_cpu != MAP_FAILED); + prime_sync_start(dma_buf_fd, false); for (i = 0; i < (width * height) / 4; i++) igt_assert_eq(ptr_cpu[i], 0); + prime_sync_end(dma_buf_fd, false); intel_copy_bo(batch, bo_1, bo_2, width * height); gem_sync(fd, bo_1->handle); @@ -93,10 +95,10 @@ static int test_read_flush(void) * until we try to read them again in step #4. This behavior could be fixed * by flush CPU read right before accessing the CPU pointer */ prime_sync_start(dma_buf_fd, false); - for (i = 0; i < (width * height) / 4; i++) if (ptr_cpu[i] != 0xc5c5c5c5) stale++; + prime_sync_end(dma_buf_fd, false); drm_intel_bo_unreference(bo_1); munmap(ptr_cpu, width * height); @@ -141,8 +143,8 @@ static int test_write_flush(void) /* This is the main point of this test: !llc hw requires a cache write * flush right here (explained in step #4). */ prime_sync_start(dma_buf_fd, true); - memset(ptr_cpu, 0x11, width * height); + prime_sync_end(dma_buf_fd, true); /* STEP #3: Copy BO 1 into BO 2, using blitter. */ bo_2 = drm_intel_bo_alloc(bufmgr, "BO 2", width * height * 4, 4096); @@ -159,10 +161,14 @@ static int test_write_flush(void) MAP_SHARED, dma_buf2_fd, 0); igt_assert(ptr2_cpu != MAP_FAILED); + prime_sync_start(dma_buf2_fd, false); + for (i = 0; i < (width * height) / 4; i++) if (ptr2_cpu[i] != 0x11111111) stale++; + prime_sync_end(dma_buf2_fd, false); + drm_intel_bo_unreference(bo_1); drm_intel_bo_unreference(bo_2); munmap(ptr_cpu, width * height); |