diff options
| author | Mengdong Lin <mengdong.lin@intel.com> | 2014-03-03 11:04:39 -0500 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2014-03-06 16:42:52 +0800 |
| commit | 92d319702553d31e70bcb1a098e896418f041a41 (patch) | |
| tree | 6f463e493df9443bbb19476d18a1749169605261 /tools/intel_audio_dump.c | |
| parent | cdf74b69c908b869e7e2daca04f49c5e5d02c097 (diff) | |
intel_audio_dump: support using base address plus an offset to dump registers
Layout of display and audio registers can be same for different Intel GPUs.
For code sharing, this patches defines functions to
- set the base address of display and audio registers
- dump registers using the base address and an offset
Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Reviewed-by: Haihao Xiang <haihao.xiang@intel.com>
Diffstat (limited to 'tools/intel_audio_dump.c')
| -rw-r--r-- | tools/intel_audio_dump.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c index 43a5bcee..47926e4d 100644 --- a/tools/intel_audio_dump.c +++ b/tools/intel_audio_dump.c @@ -37,6 +37,8 @@ static uint32_t devid; +static int aud_reg_base = 0; /* base address of audio registers */ +static int disp_reg_base = 0; /* base address of display registers */ #define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1) #define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low)) @@ -51,12 +53,33 @@ static uint32_t devid; #define OPNAME(names, index) \ names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)] +#define set_aud_reg_base(base) (aud_reg_base = (base)) + +#define set_reg_base(base, audio_offset) \ + do { \ + disp_reg_base = (base); \ + set_aud_reg_base((base) + (audio_offset)); \ + } while (0) + #define dump_reg(reg, desc) \ do { \ dword = INREG(reg); \ printf("%-21s 0x%08x %s\n", # reg, dword, desc); \ } while (0) +#define dump_disp_reg(reg, desc) \ + do { \ + dword = INREG(disp_reg_base + reg); \ + printf("%-21s 0x%08x %s\n", # reg, dword, desc); \ + } while (0) + +#define dump_aud_reg(reg, desc) \ + do { \ + dword = INREG(aud_reg_base + reg); \ + printf("%-21s 0x%08x %s\n", # reg, dword, desc); \ + } while (0) + +#define read_aud_reg(reg) INREG(aud_reg_base + (reg)) static const char * const pixel_clock[] = { [0] = "25.2 / 1.001 MHz", |