diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-12-21 14:11:36 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-12-23 16:53:59 +0200 |
| commit | 502483a39c70d2d3eb5c181133ba1048bbcc8baf (patch) | |
| tree | 77400527189dbcbf649b89837f83d0ef87ceb89a /tools/intel_display_poller.c | |
| parent | 53996d5effdb478a3796460db181d9a31e1c60f1 (diff) | |
tools/intel_display_poller: Add gen9+ support
All the registers we care about should be the same for all
bdw+ platforms, so let's just use the bdw path for gen9+.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Diffstat (limited to 'tools/intel_display_poller.c')
| -rw-r--r-- | tools/intel_display_poller.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c index 2129c613..63c930fb 100644 --- a/tools/intel_display_poller.c +++ b/tools/intel_display_poller.c @@ -515,7 +515,7 @@ static void poll_dsl_deiir(uint32_t devid, int pipe, int bit, bit = 1 << bit; dsl = PIPE_REG(pipe, PIPEA_DSL); - if (IS_GEN8(devid)) { + if (intel_gen(devid) >= 8) { iir = GEN8_DE_PIPE_IIR(pipe); ier = GEN8_DE_PIPE_IER(pipe); imr = GEN8_DE_PIPE_IMR(pipe); @@ -1152,7 +1152,7 @@ int main(int argc, char *argv[]) default: usage(argv[0]); } - } else if (IS_GEN8(devid)) { + } else if (intel_gen(devid) >= 8) { if (test_pixelcount) usage(argv[0]); |