diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-09-09 17:00:56 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-09-11 15:33:28 +0300 |
| commit | c137ac71584467424f8a7bbb40825fa6250093c5 (patch) | |
| tree | 6897b1d7cdb416ababe7e2c0526f7a085d6c984e /tools/intel_display_poller.c | |
| parent | a8b85ea21b053145527a848b51b57f5c0cfa003e (diff) | |
tools/intel_display_poller: Align DSPSURF to 128k to appease gen4/vlv/chv
gen4/vlv/chv require DSPSURF to be 128k aligned. Try to respect that
in order to avoid ugly glitches.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Diffstat (limited to 'tools/intel_display_poller.c')
| -rw-r--r-- | tools/intel_display_poller.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c index 99fd5929..a6ae8d46 100644 --- a/tools/intel_display_poller.c +++ b/tools/intel_display_poller.c @@ -314,7 +314,7 @@ static void poll_pixel_flip(uint32_t devid, int pipe, int target_pixel, int targ break; } - write_reg(surf, saved+4096); + write_reg(surf, saved+128*1024); while (!quit){ pix2 = read_reg(pix) & PIPE_PIXEL_MASK; @@ -763,7 +763,7 @@ static void poll_dsl_flip(uint32_t devid, int pipe, int target_scanline, int tar break; } - write_reg(surf, saved+4096); + write_reg(surf, saved+128*1024); while (!quit) { dsl2 = read_reg(dsl); @@ -802,7 +802,7 @@ static void poll_dsl_surflive(uint32_t devid, int pipe, saved = read_reg(surf); surf1 = saved & ~0xfff; - surf2 = surf1 + 4096; + surf2 = surf1 + 128*1024; while (!quit) { write_reg(surf, surf2); |