diff options
| author | Thomas Wood <thomas.wood@intel.com> | 2015-08-25 11:30:11 +0100 |
|---|---|---|
| committer | Thomas Wood <thomas.wood@intel.com> | 2015-09-08 16:14:45 +0100 |
| commit | af9791849467a3437e0920c8f08c5a646302da7d (patch) | |
| tree | 3f9780d54a2f52bf76823b76257713f4bbc607aa /tools/registers | |
| parent | 2142a15d49f85175677ff360833869afe9c79b58 (diff) | |
tools: remove quick_dump
Remove quick_dump as it has been replaced by the intel_reg tool and move
the register definition files to tools/registers.
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'tools/registers')
33 files changed, 2711 insertions, 0 deletions
diff --git a/tools/registers/Makefile.am b/tools/registers/Makefile.am new file mode 100644 index 00000000..4e1e3c2f --- /dev/null +++ b/tools/registers/Makefile.am @@ -0,0 +1 @@ +EXTRA_DIST = ${REGISTERS_EXTRA_DIST} diff --git a/tools/registers/audio_config_haswell_plus.txt b/tools/registers/audio_config_haswell_plus.txt new file mode 100644 index 00000000..f3fbb67e --- /dev/null +++ b/tools/registers/audio_config_haswell_plus.txt @@ -0,0 +1,35 @@ +('AUD_TCA_CONFIG', '0x00065000', '') +('AUD_TCB_CONFIG', '0x00065100', '') +('AUD_TCC_CONFIG', '0x00065200', '') +('AUD_C1_MISC_CTRL', '0x00065010', '') +('AUD_C2_MISC_CTRL', '0x00065110', '') +('AUD_C3_MISC_CTRL', '0x00065210', '') +('AUD_VID_DID', '0x00065020', '') +('AUD_RID', '0x00065024', '') +('AUD_TCA_M_CTS_ENABLE', '0x00065028', '') +('AUD_TCB_M_CTS_ENABLE', '0x00065128', '') +('AUD_TCC_M_CTS_ENABLE', '0x00065228', '') +('AUD_PWRST', '0x0006504C', '') +('AUD_TCA_EDID_DATA', '0x00065050', '') +('AUD_TCB_EDID_DATA', '0x00065150', '') +('AUD_TCC_EDID_DATA', '0x00065250', '') +('AUD_TCA_INFOFR', '0x00065054', '') +('AUD_TCB_INFOFR', '0x00065154', '') +('AUD_TCC_INFOFR', '0x00065254', '') +('AUD_PIPE_CONV_CFG', '0x0006507C', '') +('AUD_C1_DIG_CNVT', '0x00065080', '') +('AUD_C2_DIG_CNVT', '0x00065180', '') +('AUD_C3_DIG_CNVT', '0x00065280', '') +('AUD_C1_STR_DESC', '0x00065084', '') +('AUD_C2_STR_DESC', '0x00065184', '') +('AUD_C3_STR_DESC', '0x00065284', '') +('AUD_OUT_CHAN_MAP', '0x00065088', '') +('AUD_TCA_PIN_PIPE_CONN_ENTRY_LENGTH', '0x000650A8', '') +('AUD_TCB_PIN_PIPE_CONN_ENTRY_LENGTH', '0x000651A8', '') +('AUD_TCC_PIN_PIPE_CONN_ENTRY_LENGTH', '0x000652A8', '') +('AUD_PIPE_CONN_SEL_CTRL', '0x000650AC', '') +('AUD_TCA_DIP_ELD_CTRL_ST', '0x000650B4', '') +('AUD_TCB_DIP_ELD_CTRL_ST', '0x000651B4', '') +('AUD_TCC_DIP_ELD_CTRL_ST', '0x000652B4', '') +('AUD_PIN_ELD_CP_VLD', '0x000650C0', '') +('AUD_HDMI_FIFO_STATUS', '0x000650D4', '') diff --git a/tools/registers/audio_debug_haswell_plus.txt b/tools/registers/audio_debug_haswell_plus.txt new file mode 100644 index 00000000..9d498bc5 --- /dev/null +++ b/tools/registers/audio_debug_haswell_plus.txt @@ -0,0 +1,8 @@ +('AUD_ICOI', '0x00065f00', '') +('AUD_IRII', '0x00065f04', '') +('AUD_ICS', '0x00065f08', '') +('AUD_CHICKENBIT_REG', '0x00065f10', '') +('AUD_DP_DIP_STATUS', '0x00065f20', '') +('AUD_TCA_M_CTS', '0x00065f44', '') +('AUD_TCB_M_CTS', '0x00065f54', '') +('AUD_TCC_M_CTS', '0x00065f64', '') diff --git a/tools/registers/base_interrupt.txt b/tools/registers/base_interrupt.txt new file mode 100644 index 00000000..df4244ba --- /dev/null +++ b/tools/registers/base_interrupt.txt @@ -0,0 +1,20 @@ +('GEN6_PMINTRMSK', '0x0000a168', '') +('DEISR', '0x00044000', '') +('DEIMR', '0x00044004', '') +('DEIIR', '0x00044008', '') +('DEIER', '0x0004400c', '') +('GTISR', '0x00044010', '') +('GTIMR', '0x00044014', '') +('GTIIR', '0x00044018', '') +('GTIER', '0x0004401c', '') +('GEN6_PMISR', '0x00044020', '') +('GEN6_PMIMR', '0x00044024', '') +('GEN6_PMIIR', '0x00044028', '') +('GEN6_PMIER', '0x0004402c', '') +('SDEISR', '0x000c4000', '') +('SDEIMR', '0x000c4004', '') +('SDEIIR', '0x000c4008', '') +('SDEIER', '0x000c400c', '') +('RENDER_IMR', '0x000020a8', '') +('BSD_IMR', '0x000120a8', '') +('BLT_IMR', '0x000220a8', '') diff --git a/tools/registers/base_other.txt b/tools/registers/base_other.txt new file mode 100644 index 00000000..5447b413 --- /dev/null +++ b/tools/registers/base_other.txt @@ -0,0 +1,7 @@ +('PGETBL_CTL', '0x00002020', '') +('MI_MODE', '0x0000209c', '') +('CCID', '0x00002180', '') +('ERROR_GEN6', '0x000040a0', '') +('RENDER_HWSTAM', '0x00002098', '') +('GEN6_BSD_HWSTAM', '0x00012098', '') +('GEN6_BLITTER_HWSTAM', '0x00022098', '') diff --git a/tools/registers/base_power.txt b/tools/registers/base_power.txt new file mode 100644 index 00000000..4a142e52 --- /dev/null +++ b/tools/registers/base_power.txt @@ -0,0 +1,21 @@ +('GEN6_RPNSWREQ', '0x0000a008', '') +('GEN6_RC_VIDEO_FREQ', '0x0000a00c', '') +('GEN6_RP_DOWN_TIMEOUT', '0x0000a010', '') +('GEN6_RP_INTERRUPT_LIMITS', '0x0000a014', '') +('GEN6_RP_CONTROL', '0x0000a024', '') +('GEN6_RP_UP_THRESHOLD', '0x0000a02c', '') +('GEN6_RP_UP_EI', '0x0000a068', '') +('GEN6_RP_DOWN_EI', '0x0000a06c', '') +('GEN6_RP_IDLE_HYSTERSIS', '0x0000a070', '') +('GEN6_RC_CONTROL', '0x0000a090', '') +('GEN6_RC_STATE', '0x0000a094', '') +('GEN6_RC1_WAKE_RATE_LIMIT', '0x0000a098', '') +('GEN6_RC6_WAKE_RATE_LIMIT', '0x0000a09c', '') +('GEN6_RC_EVALUATION_INTERVAL', '0x0000a0a8', '') +('GEN6_RC_IDLE_HYSTERSIS', '0x0000a0ac', '') +('GEN6_RC_SLEEP', '0x0000a0b0', '') +('GEN6_RC1e_THRESHOLD', '0x0000a0b4', '') +('GEN6_RC6_THRESHOLD', '0x0000a0b8', '') +('RC6_RESIDENCY_TIME', '0x00138108', '') +('RC6p_RESIDENCY_TIME', '0x0013810c', '') +('RC6pp_RESIDENCY_TIME', '0x00138110', '') diff --git a/tools/registers/base_rings.txt b/tools/registers/base_rings.txt new file mode 100644 index 00000000..f2d6576d --- /dev/null +++ b/tools/registers/base_rings.txt @@ -0,0 +1,33 @@ +('RENDER_INSTPM', '0x20c0', '') +('BSD_INSTPM', '0x120c0', '') +('BLT_INSTPM', '0x220c0', '') +('RENDER_RING_TAIL', '0x2030', '') +('BSD_RING_TAIL', '0x12030', '') +('BLT_RING_TAIL', '0x22030', '') +('RENDER_RING_HEAD', '0x2034', '') +('BSD_RING_HEAD', '0x12034', '') +('BLT_RING_HEAD', '0x22034', '') +('RENDER_RING_START', '0x2038', '') +('BSD_RING_START', '0x12038', '') +('BLT_RING_START', '0x22038', '') +('RENDER_RING_CTL', '0x203c', '') +('BSD_RING_CTL', '0x1203c', '') +('BLT_RING_CTL', '0x2203c', '') +('RENDER_IPEIR', '0x2064', '') +('BSD_IPEIR', '0x12064', '') +('BLT_IPEIR', '0x22064', '') +('RENDER_IPEHR', '0x2068', '') +('BSD_IPEHR', '0x12068', '') +('BLT_IPEHR', '0x22068', '') +('RENDER_INSTDONE', '0x206c', '') +('BSD_INSTDONE', '0x1206c', '') +('BLT_INSTDONE', '0x2206c', '') +('RENDER_INSTPS', '0x2070', '') +('BSD_INSTPS', '0x12070', '') +('BLT_INSTPS', '0x22070', '') +('RENDER_RING_ACTHD', '0x2074', '') +('BSD_RING_ACTHD', '0x12074', '') +('BLT_RING_ACTHD', '0x22074', '') +('RENDER_FADDR', '0x2078', '') +('BSD_FADDR', '0x12078', '') +('BLT_FADDR', '0x22078', '') diff --git a/tools/registers/broadwell b/tools/registers/broadwell new file mode 100644 index 00000000..7888a36b --- /dev/null +++ b/tools/registers/broadwell @@ -0,0 +1,7 @@ +common_display.txt +gen7_other.txt +haswell_other.txt +gen8_interrupt.txt +gen8_other.txt +audio_config_haswell_plus.txt +audio_debug_haswell_plus.txt diff --git a/tools/registers/cherryview b/tools/registers/cherryview new file mode 100644 index 00000000..a86abe25 --- /dev/null +++ b/tools/registers/cherryview @@ -0,0 +1,8 @@ +vlv_pipe_a.txt +vlv_pipe_b.txt +chv_pipe_c.txt +chv_display_base.txt +chv_dpio_phy_x2.txt +chv_dpio_phy_x1.txt +vlv_dsi.txt +gen7_other.txt diff --git a/tools/registers/chv_display_base.txt b/tools/registers/chv_display_base.txt new file mode 100644 index 00000000..8b1d495f --- /dev/null +++ b/tools/registers/chv_display_base.txt @@ -0,0 +1,211 @@ +('DPFLIPSTAT', '0x70028', '0x180000') +('DPINVGTT', '0x7002C', '0x180000') + +('DSPARB', '0x70030', '0x180000') +('DSPARB2', '0x70060', '0x180000') +('DSPARB3', '0x7006C', '0x180000') + +('DSPHOWM', '0x70064', '0x180000') +('DSPHOWM1', '0x70068', '0x180000') +('FW1', '0x70034', '0x180000') +('FW2', '0x70038', '0x180000') +('FW3', '0x7003C', '0x180000') +('FW4', '0x70070', '0x180000') +('FW5', '0x70074', '0x180000') +('FW6', '0x70078', '0x180000') +('FW7', '0x7007C', '0x180000') +('FW8', '0x700B8', '0x180000') +('FW9', '0x700BC', '0x180000') + +('DDL1', '0x70050', '0x180000') +('DDL2', '0x70054', '0x180000') +('DDL3', '0x70058', '0x180000') + +('VGACNTRL', '0x71400', '0x180000') + +('CBR1', '0x70400', '0x180000') +('CBR2', '0x70404', '0x180000') +('CBR3', '0x7040C', '0x180000') +('CBR4', '0x70450', '0x180000') +('CCBR', '0x70408', '0x180000') + +('SWF00', '0x70410', '0x180000') +('SWF01', '0x70414', '0x180000') +('SWF02', '0x70418', '0x180000') +('SWF03', '0x7041C', '0x180000') +('SWF04', '0x70420', '0x180000') +('SWF05', '0x70424', '0x180000') +('SWF06', '0x70428', '0x180000') +('SWF07', '0x7042C', '0x180000') +('SWF08', '0x70430', '0x180000') +('SWF09', '0x70434', '0x180000') +('SWF0A', '0x70438', '0x180000') +('SWF0B', '0x7043C', '0x180000') +('SWF0C', '0x70440', '0x180000') +('SWF0D', '0x70444', '0x180000') +('SWF0E', '0x70448', '0x180000') +('SWF0F', '0x7044C', '0x180000') +('SWF10', '0x71410', '0x180000') +('SWF11', '0x71414', '0x180000') +('SWF12', '0x71418', '0x180000') +('SWF13', '0x7141C', '0x180000') +('SWF14', '0x71420', '0x180000') +('SWF15', '0x71424', '0x180000') +('SWF16', '0x71428', '0x180000') +('SWF17', '0x7142C', '0x180000') +('SWF18', '0x71430', '0x180000') +('SWF19', '0x71434', '0x180000') +('SWF1A', '0x71438', '0x180000') +('SWF1B', '0x7143C', '0x180000') +('SWF1C', '0x71440', '0x180000') +('SWF1D', '0x71444', '0x180000') +('SWF1E', '0x71448', '0x180000') +('SWF1F', '0x7144C', '0x180000') +('SWF30', '0x72414', '0x180000') +('SWF31', '0x72418', '0x180000') +('SWF32', '0x7241C', '0x180000') + +('PCSRC', '0x73000', '0x180000') +('PCSTAT', '0x73004', '0x180000') +('PCSRC2', '0x73008', '0x180000') +('PCSTAT2', '0x7300C', '0x180000') +('PCSRC3', '0x73010', '0x180000') +('PCSTAT3', '0x73014', '0x180000') + +('PFIT_CONTROL', '0x61230', '0x180000') +('PFIT_PGM_RATIOS', '0x61234', '0x180000') +('PFIT_AUTO_RATION', '0x61238', '0x180000') +('PFIT_INIT_PHASE', '0x6123C', '0x180000') + +('GPIOCTL_0', '0x5010', '0x180000') +('GPIOCTL_1', '0x5014', '0x180000') +('GPIOCTL_2', '0x5018', '0x180000') +('GPIOCTL_3', '0x501C', '0x180000') +('GPIOCTL_4', '0x5020', '0x180000') + +('GMBUS0', '0x5100', '0x180000') +('GMBUS1', '0x5104', '0x180000') +('GMBUS2', '0x5108', '0x180000') +('GMBUS3', '0x510C', '0x180000') +('GMBUS4', '0x5110', '0x180000') +('GMBUS5', '0x5120', '0x180000') +('GMBUS6', '0x5130', '0x180000') +('GMBUS7', '0x5134', '0x180000') + +('RAWCLK_FREQ', '0x6024', '0x180000') +('GMBUSFREQ', '0x6510', '0x180000') +('DSPCLK_GATE_D', '0x6200', '0x180000') +('DSPCLK1_GATE_D', '0x6034', '0x180000') +('RAMCLK_GATE_D', '0x6210', '0x180000') +('D_STATE', '0x6104', '0x180000') +('DPPSR_CGDIS', '0x6204', '0x180000') +('DPPSR1_CGDIS', '0x6220', '0x180000') +('FW_BLC_SELF', '0x6500', '0x180000') +('MI_ARB', '0x6504', '0x180000') +('CZCLK_CDCLK_FREQ_RATIO', '0x6508', '0x180000') +('GCI_CONTROL', '0x650C', '0x180000') +('DOT_MIPI', '0x6038', '0x180000') + +('PORT_HOTPLUG_EN', '0x61110', '0x180000') +('PORT_HOTPLUG_STAT', '0x61114', '0x180000') +('HPD_LONG_VALUE', '0x61120', '0x180000') +('HPD_FILTER_VALUE', '0x61124', '0x180000') + +('HDMIB', '0x61140', '0x180000') +('HDMIC', '0x61160', '0x180000') +('HDMID', '0x6116C', '0x180000') + +('DP2', '0x61154', '0x180000') +('DIGITAL_HPD_CTRL', '0x61164', '0x180000') +('DV_DETERM', '0x61168', '0x180000') + +('DP_AUX_CH_AKSV_HI', '0x64130', '0x180000') +('DP_AUX_CH_AKSV_LO', '0x64134', '0x180000') + +('DP_B', '0x64100', '0x180000') +('DPB_AUX_CH_CTL', '0x64110', '0x180000') +('DPB_AUX_CH_DATA1', '0x64114', '0x180000') +('DPB_AUX_CH_DATA2', '0x64118', '0x180000') +('DPB_AUX_CH_DATA3', '0x6411C', '0x180000') +('DPB_AUX_CH_DATA4', '0x64120', '0x180000') +('DPB_AUX_CH_DATA5', '0x64124', '0x180000') +('DPB_AUX_TST', '0x64150', '0x180000') + +('DP_C', '0x64200', '0x180000') +('DPC_AUX_CH_CTL', '0x64210', '0x180000') +('DPC_AUX_CH_DATA1', '0x64214', '0x180000') +('DPC_AUX_CH_DATA2', '0x64218', '0x180000') +('DPC_AUX_CH_DATA3', '0x6421C', '0x180000') +('DPC_AUX_CH_DATA4', '0x64220', '0x180000') +('DPC_AUX_CH_DATA5', '0x64224', '0x180000') +('DPC_AUX_TST', '0x64228', '0x180000') + +('DP_D', '0x64300', '0x180000') +('DPD_AUX_CH_CTL', '0x64310', '0x180000') +('DPD_AUX_CH_DATA1', '0x64314', '0x180000') +('DPD_AUX_CH_DATA2', '0x64318', '0x180000') +('DPD_AUX_CH_DATA3', '0x6431C', '0x180000') +('DPD_AUX_CH_DATA4', '0x64320', '0x180000') +('DPD_AUX_CH_DATA5', '0x64324', '0x180000') +('DPD_AUX_TST', '0x64328', '0x180000') + +('DPIO_PHY_CONTROL', '0x60100', '0x180000') +('DPIO_PHY_GPIO_DATA', '0x60108', '0x180000') +('DPIO_PHY_STATUS', '0x6240', '0x180000') +('DPIO_PHY_STATUS1', '0x60104', '0x180000') +('DPIO_PHY_STATUS2', '0x6010C', '0x180000') + +('DPIO_BONUS0', '0x64138', '0x180000') +('DPIO_BONUS1', '0x6413C', '0x180000') +('DPIO_BONUS2', '0x64140', '0x180000') +('DPIO_BONUS0_READ_BACK', '0x64144', '0x180000') +('DPIO_BONUS1_READ_BACK', '0x64148', '0x180000') +('DPIO_BONUS2_READ_BACK', '0x6414C', '0x180000') + +('DPA_PIX_GEN_CTRL', '0x61198', '0x180000') +('DPA_PROG_PIXEL_DATA_1', '0x6119C', '0x180000') +('DPA_PROG_PIXEL_DATA_2', '0x611A0', '0x180000') +('DPA_PROG_PIXEL_DATA_3', '0x611A4', '0x180000') +('DPA_PROG_PIXEL_DATA_4', '0x611A8', '0x180000') + +('DPB_PIX_GEN_CTRL', '0x611B0', '0x180000') +('DPB_PROG_PIXEL_DATA_1', '0x611B4', '0x180000') +('DPB_PROG_PIXEL_DATA_2', '0x611B8', '0x180000') +('DPB_PROG_PIXEL_DATA_3', '0x611BC', '0x180000') +('DPB_PROG_PIXEL_DATA_4', '0x611C0', '0x180000') + +('DPC_PIX_GEN_CTRL', '0x611D0', '0x180000') +('DPC_PROG_PIXEL_DATA_1', '0x611D4', '0x180000') +('DPC_PROG_PIXEL_DATA_2', '0x611D8', '0x180000') +('DPC_PROG_PIXEL_DATA_3', '0x611DC', '0x180000') +('DPC_PROG_PIXEL_DATA_4', '0x611E0', '0x180000') + +('AUD_VID_DID', '0x62020', '0x180000') +('AUD_RID', '0x62024', '0x180000') +('AUD_PWRST', '0x6204C', '0x180000') +('AUD_PORT_EN_HD_CFG', '0x6207C', '0x180000') +('AUD_OUT_CH_STR', '0x62088', '0x180000') +('AUD_PINW_CONNLNG_LIST', '0x620A8', '0x180000') +('AUD_PINW_CONNLNG_SEL', '0x620AC', '0x180000') +('AUD_CNTL_ST2', '0x620C0', '0x180000') +('AUD_HDMIW_STATUS', '0x620D4', '0x180000') +('AUD_SSID_DBG', '0x62F00', '0x180000') +('AUD_PWST1_DBG', '0x62F04', '0x180000') +('AUD_PWST2_DBG', '0x62F14', '0x180000') +('AUD_PORT_EN_B_DBG', '0x62F20', '0x180000') +('AUD_PWST3_DBG', '0x62F24', '0x180000') +('AUD_PORT_EN_C_DBG', '0x62F28', '0x180000') +('AUD_PORT_EN_D_DBG', '0x62F2C', '0x180000') +('AUD_CHICKENBIT', '0x62F38', '0x180000') +('AUD_CNTL_ST_B_DBG', '0x62F60', '0x180000') +('AUD_HDMIW_INFOFR_B_DBG', '0x62F64', '0x180000') +('AUD_CNTL_ST_C_DBG', '0x62F70', '0x180000') +('AUD_HDMIW_INFOFR_C_DBG', '0x62F74', '0x180000') +('AUD_CNTL_ST_D_DBG', '0x62F80', '0x180000') +('AUD_HDMIW_INFOFR_D_DBG', '0x62F84', '0x180000') +('AUD_CONFIG_DEFAULT2_REG_PORTB', '0x62F88', '0x180000') +('AUD_CONFIG_DEFAULT2_REG_PORTC', '0x62F8C', '0x180000') +('AUD_CONFIG_DEFAULT2_REG_PORTD', '0x62F90', '0x180000') +('AUD_MCTSA', '0x62F94', '0x180000') +('AUD_MCTSB', '0x62F98', '0x180000') +('AUD_MCTSC', '0x62F9C', '0x180000') diff --git a/tools/registers/chv_dpio_phy_x1.txt b/tools/registers/chv_dpio_phy_x1.txt new file mode 100644 index 00000000..7b08a2d8 --- /dev/null +++ b/tools/registers/chv_dpio_phy_x1.txt @@ -0,0 +1,216 @@ +('PLL1_DW0', '0x8000', 'DPIO') +('PLL1_DW1', '0x8004', 'DPIO') +('PLL1_DW2', '0x8008', 'DPIO') +('PLL1_DW3', '0x800C', 'DPIO') +('PLL1_DW4', '0x8010', 'DPIO') +('PLL1_DW5', '0x8014', 'DPIO') +('PLL1_DW6', '0x8018', 'DPIO') +('PLL1_DW7', '0x801C', 'DPIO') +('PLL1_DW8', '0x8020', 'DPIO') +('PLL1_DW9', '0x8024', 'DPIO') +('PLL1_DW10', '0x8028', 'DPIO') +('PLL1_DW11', '0x802C', 'DPIO') +('PLL1_DW12', '0x8030', 'DPIO') +('PLL1_DW13', '0x8034', 'DPIO') +('PLL1_DW14', '0x8038', 'DPIO') +('PLL1_DW15', '0x803C', 'DPIO') +('PLL1_DW16', '0x8040', 'DPIO') +('PLL1_DW17', '0x8044', 'DPIO') +('PLL1_DW18', '0x8048', 'DPIO') +('PLL1_DW19', '0x804C', 'DPIO') +('PLL1_DW20', '0x8050', 'DPIO') +('PLL1_DW21', '0x8054', 'DPIO') +('PLL1_DW22', '0x8058', 'DPIO') +('PLL1_DW23', '0x805C', 'DPIO') +('PLL1_DW24', '0x8060', 'DPIO') +('PLL1_DW25', '0x8064', 'DPIO') +('PLL1_DW26', '0x8068', 'DPIO') +('PLL1_DW27', '0x806C', 'DPIO') +('PLL1_DW28', '0x8070', 'DPIO') +('PLL1_DW29', '0x8074', 'DPIO') +('PLL1_DW30', '0x8078', 'DPIO') +('PLL1_DW31', '0x807C', 'DPIO') +('REF_DW0', '0x80A0', 'DPIO') +('REF_DW1', '0x80A4', 'DPIO') +('REF_DW2', '0x80A8', 'DPIO') +('REF_DW3', '0x80AC', 'DPIO') +('REF_DW4', '0x80B0', 'DPIO') +('REF_DW5', '0x80B4', 'DPIO') +('REF_DW6', '0x80B8', 'DPIO') +('REF_DW7', '0x80BC', 'DPIO') +('REF_DW8', '0x80C0', 'DPIO') +('REF_DW9', '0x80C4', 'DPIO') +('REF_DW10', '0x80C8', 'DPIO') +('REF_DW11', '0x80CC', 'DPIO') +('REF_DW12', '0x80D0', 'DPIO') +('REF_DW13', '0x80D4', 'DPIO') +('REF_DW14', '0x80D8', 'DPIO') +('REF_DW15', '0x80DC', 'DPIO') +('CL1_DW0', '0x8100', 'DPIO') +('CL1_DW1', '0x8104', 'DPIO') +('CL1_DW2', '0x8108', 'DPIO') +('CL1_DW3', '0x810C', 'DPIO') +('CL1_DW4', '0x8110', 'DPIO') +('CL1_DW5', '0x8114', 'DPIO') +('CL1_DW6', '0x8118', 'DPIO') +('CL1_DW7', '0x811C', 'DPIO') +('CL1_DW8', '0x8120', 'DPIO') +('CL1_DW9', '0x8124', 'DPIO') +('CL1_DW10', '0x8128', 'DPIO') +('CL1_DW11', '0x812C', 'DPIO') +('CL1_DW12', '0x8130', 'DPIO') +('CL1_DW13', '0x8134', 'DPIO') +('CL1_DW14', '0x8138', 'DPIO') +('CL1_DW15', '0x813C', 'DPIO') +('CL1_DW16', '0x8140', 'DPIO') +('CL1_DW17', '0x8144', 'DPIO') +('CL1_DW18', '0x8148', 'DPIO') +('CL1_DW19', '0x814C', 'DPIO') +('CL1_DW20', '0x8150', 'DPIO') +('CL1_DW21', '0x8154', 'DPIO') +('CL1_DW22', '0x8158', 'DPIO') +('CL1_DW23', '0x815C', 'DPIO') +('CL1_DW24', '0x8160', 'DPIO') +('CL1_DW25', '0x8164', 'DPIO') +('CL1_DW26', '0x8168', 'DPIO') +('CL1_DW27', '0x816C', 'DPIO') +('CL1_DW28', '0x8170', 'DPIO') +('CL1_DW29', '0x8174', 'DPIO') +('CL1_DW30', '0x8178', 'DPIO') +('CL1_DW31', '0x817C', 'DPIO') +('PCS01_CH0_DW0', '0x0200', 'DPIO') +('PCS01_CH0_DW1', '0x0204', 'DPIO') +('PCS01_CH0_DW2', '0x0208', 'DPIO') +('PCS01_CH0_DW3', '0x020C', 'DPIO') +('PCS01_CH0_DW4', '0x0210', 'DPIO') +('PCS01_CH0_DW5', '0x0214', 'DPIO') +('PCS01_CH0_DW6', '0x0218', 'DPIO') +('PCS01_CH0_DW7', '0x021C', 'DPIO') +('PCS01_CH0_DW8', '0x0220', 'DPIO') +('PCS01_CH0_DW9', '0x0224', 'DPIO') +('PCS01_CH0_DW10', '0x0228', 'DPIO') +('PCS01_CH0_DW11', '0x022C', 'DPIO') +('PCS01_CH0_DW12', '0x0230', 'DPIO') +('PCS01_CH0_DW13', '0x0234', 'DPIO') +('PCS01_CH0_DW14', '0x0238', 'DPIO') +('PCS01_CH0_DW15', '0x023C', 'DPIO') +('PCS01_CH0_DW16', '0x0240', 'DPIO') +('PCS01_CH0_DW17', '0x0244', 'DPIO') +('PCS01_CH0_DW18', '0x0248', 'DPIO') +('PCS01_CH0_DW19', '0x024C', 'DPIO') +('PCS01_CH0_DW20', '0x0250', 'DPIO') +('PCS01_CH0_DW21', '0x0254', 'DPIO') +('PCS01_CH0_DW22', '0x0258', 'DPIO') +('PCS01_CH0_DW23', '0x025C', 'DPIO') +('PCS01_CH0_DW24', '0x0260', 'DPIO') +('PCS01_CH0_DW25', '0x0264', 'DPIO') +('TX0_CH0_DW0', '0x0080', 'DPIO') +('TX0_CH0_DW1', '0x0084', 'DPIO') +('TX0_CH0_DW2', '0x0088', 'DPIO') +('TX0_CH0_DW3', '0x008C', 'DPIO') +('TX0_CH0_DW4', '0x0090', 'DPIO') +('TX0_CH0_DW5', '0x0094', 'DPIO') +('TX0_CH0_DW6', '0x0098', 'DPIO') +('TX0_CH0_DW7', '0x009C', 'DPIO') +('TX0_CH0_DW8', '0x00A0', 'DPIO') +('TX0_CH0_DW9', '0x00A4', 'DPIO') +('TX0_CH0_DW10', '0x00A8', 'DPIO') +('TX0_CH0_DW11', '0x00AC', 'DPIO') +('TX0_CH0_DW12', '0x00B0', 'DPIO') +('TX0_CH0_DW13', '0x00B4', 'DPIO') +('TX0_CH0_DW14', '0x00B8', 'DPIO') +('TX0_CH0_DW15', '0x00BC', 'DPIO') +('TX0_CH0_DW16', '0x00C0', 'DPIO') +('TX0_CH0_DW17', '0x00C4', 'DPIO') +('TX0_CH0_DW18', '0x00C8', 'DPIO') +('TX0_CH0_DW19', '0x00CC', 'DPIO') +('TX0_CH0_DW20', '0x00D0', 'DPIO') +('TX1_CH0_DW0', '0x0280', 'DPIO') +('TX1_CH0_DW1', '0x0284', 'DPIO') +('TX1_CH0_DW2', '0x0288', 'DPIO') +('TX1_CH0_DW3', '0x028C', 'DPIO') +('TX1_CH0_DW4', '0x0290', 'DPIO') +('TX1_CH0_DW5', '0x0294', 'DPIO') +('TX1_CH0_DW6', '0x0298', 'DPIO') +('TX1_CH0_DW7', '0x029C', 'DPIO') +('TX1_CH0_DW8', '0x02A0', 'DPIO') +('TX1_CH0_DW9', '0x02A4', 'DPIO') +('TX1_CH0_DW10', '0x02A8', 'DPIO') +('TX1_CH0_DW11', '0x02AC', 'DPIO') +('TX1_CH0_DW12', '0x02B0', 'DPIO') +('TX1_CH0_DW13', '0x02B4', 'DPIO') +('TX1_CH0_DW14', '0x02B8', 'DPIO') +('TX1_CH0_DW15', '0x02BC', 'DPIO') +('TX1_CH0_DW16', '0x02C0', 'DPIO') +('TX1_CH0_DW17', '0x02C4', 'DPIO') +('TX1_CH0_DW18', '0x02C8', 'DPIO') +('TX1_CH0_DW19', '0x02CC', 'DPIO') +('TX1_CH0_DW20', '0x02D0', 'DPIO') +('PCS23_CH0_DW0', '0x0400', 'DPIO') +('PCS23_CH0_DW1', '0x0404', 'DPIO') +('PCS23_CH0_DW2', '0x0408', 'DPIO') +('PCS23_CH0_DW3', '0x040C', 'DPIO') +('PCS23_CH0_DW4', '0x0410', 'DPIO') +('PCS23_CH0_DW5', '0x0414', 'DPIO') +('PCS23_CH0_DW6', '0x0418', 'DPIO') +('PCS23_CH0_DW7', '0x041C', 'DPIO') +('PCS23_CH0_DW8', '0x0420', 'DPIO') +('PCS23_CH0_DW9', '0x0424', 'DPIO') +('PCS23_CH0_DW10', '0x0428', 'DPIO') +('PCS23_CH0_DW11', '0x042C', 'DPIO') +('PCS23_CH0_DW12', '0x0430', 'DPIO') +('PCS23_CH0_DW13', '0x0434', 'DPIO') +('PCS23_CH0_DW14', '0x0438', 'DPIO') +('PCS23_CH0_DW15', '0x043C', 'DPIO') +('PCS23_CH0_DW16', '0x0440', 'DPIO') +('PCS23_CH0_DW17', '0x0444', 'DPIO') +('PCS23_CH0_DW18', '0x0448', 'DPIO') +('PCS23_CH0_DW19', '0x044C', 'DPIO') +('PCS23_CH0_DW20', '0x0450', 'DPIO') +('PCS23_CH0_DW21', '0x0454', 'DPIO') +('PCS23_CH0_DW22', '0x0458', 'DPIO') +('PCS23_CH0_DW23', '0x045C', 'DPIO') +('PCS23_CH0_DW24', '0x0460', 'DPIO') +('PCS23_CH0_DW25', '0x0464', 'DPIO') +('TX2_CH0_DW0', '0x0480', 'DPIO') +('TX2_CH0_DW1', '0x0484', 'DPIO') +('TX2_CH0_DW2', '0x0488', 'DPIO') +('TX2_CH0_DW3', '0x048C', 'DPIO') +('TX2_CH0_DW4', '0x0490', 'DPIO') +('TX2_CH0_DW5', '0x0494', 'DPIO') +('TX2_CH0_DW6', '0x0498', 'DPIO') +('TX2_CH0_DW7', '0x049C', 'DPIO') +('TX2_CH0_DW8', '0x04A0', 'DPIO') +('TX2_CH0_DW9', '0x04A4', 'DPIO') +('TX2_CH0_DW10', '0x04A8', 'DPIO') +('TX2_CH0_DW11', '0x04AC', 'DPIO') +('TX2_CH0_DW12', '0x04B0', 'DPIO') +('TX2_CH0_DW13', '0x04B4', 'DPIO') +('TX2_CH0_DW14', '0x04B8', 'DPIO') +('TX2_CH0_DW15', '0x04BC', 'DPIO') +('TX2_CH0_DW16', '0x04C0', 'DPIO') +('TX2_CH0_DW17', '0x04C4', 'DPIO') +('TX2_CH0_DW18', '0x04C8', 'DPIO') +('TX2_CH0_DW19', '0x04CC', 'DPIO') +('TX2_CH0_DW20', '0x04D0', 'DPIO') +('TX3_CH0_DW0', '0x0680', 'DPIO') +('TX3_CH0_DW1', '0x0684', 'DPIO') +('TX3_CH0_DW2', '0x0688', 'DPIO') +('TX3_CH0_DW3', '0x068C', 'DPIO') +('TX3_CH0_DW4', '0x0690', 'DPIO') +('TX3_CH0_DW5', '0x0694', 'DPIO') +('TX3_CH0_DW6', '0x0698', 'DPIO') +('TX3_CH0_DW7', '0x069C', 'DPIO') +('TX3_CH0_DW8', '0x06A0', 'DPIO') +('TX3_CH0_DW9', '0x06A4', 'DPIO') +('TX3_CH0_DW10', '0x06A8', 'DPIO') +('TX3_CH0_DW11', '0x06AC', 'DPIO') +('TX3_CH0_DW12', '0x06B0', 'DPIO') +('TX3_CH0_DW13', '0x06B4', 'DPIO') +('TX3_CH0_DW14', '0x06B8', 'DPIO') +('TX3_CH0_DW15', '0x06BC', 'DPIO') +('TX3_CH0_DW16', '0x06C0', 'DPIO') +('TX3_CH0_DW17', '0x06C4', 'DPIO') +('TX3_CH0_DW18', '0x06C8', 'DPIO') +('TX3_CH0_DW19', '0x06CC', 'DPIO') +('TX3_CH0_DW20', '0x06D0', 'DPIO') diff --git a/tools/registers/chv_dpio_phy_x2.txt b/tools/registers/chv_dpio_phy_x2.txt new file mode 100644 index 00000000..1dd8f684 --- /dev/null +++ b/tools/registers/chv_dpio_phy_x2.txt @@ -0,0 +1,392 @@ +('PLL1_DW0', '0x8000', 'DPIO2') +('PLL1_DW1', '0x8004', 'DPIO2') +('PLL1_DW2', '0x8008', 'DPIO2') +('PLL1_DW3', '0x800C', 'DPIO2') +('PLL1_DW4', '0x8010', 'DPIO2') +('PLL1_DW5', '0x8014', 'DPIO2') +('PLL1_DW6', '0x8018', 'DPIO2') +('PLL1_DW7', '0x801C', 'DPIO2') +('PLL1_DW8', '0x8020', 'DPIO2') +('PLL1_DW9', '0x8024', 'DPIO2') +('PLL1_DW10', '0x8028', 'DPIO2') +('PLL1_DW11', '0x802C', 'DPIO2') +('PLL1_DW12', '0x8030', 'DPIO2') +('PLL1_DW13', '0x8034', 'DPIO2') +('PLL1_DW14', '0x8038', 'DPIO2') +('PLL1_DW15', '0x803C', 'DPIO2') +('PLL1_DW16', '0x8040', 'DPIO2') +('PLL1_DW17', '0x8044', 'DPIO2') +('PLL1_DW18', '0x8048', 'DPIO2') +('PLL1_DW19', '0x804C', 'DPIO2') +('PLL1_DW20', '0x8050', 'DPIO2') +('PLL1_DW21', '0x8054', 'DPIO2') +('PLL1_DW22', '0x8058', 'DPIO2') +('PLL1_DW23', '0x805C', 'DPIO2') +('PLL1_DW24', '0x8060', 'DPIO2') +('PLL1_DW25', '0x8064', 'DPIO2') +('PLL1_DW26', '0x8068', 'DPIO2') +('PLL1_DW27', '0x806C', 'DPIO2') +('PLL1_DW28', '0x8070', 'DPIO2') +('PLL1_DW29', '0x8074', 'DPIO2') +('PLL1_DW30', '0x8078', 'DPIO2') +('PLL1_DW31', '0x807C', 'DPIO2') +('CL2_DW0', '0x8080', 'DPIO2') +('CL2_DW1', '0x8084', 'DPIO2') +('CL2_DW2', '0x8088', 'DPIO2') +('CL2_DW3', '0x808C', 'DPIO2') +('CL2_DW4', '0x8090', 'DPIO2') +('CL2_DW5', '0x8094', 'DPIO2') +('CL2_DW6', '0x8098', 'DPIO2') +('CL2_DW7', '0x809C', 'DPIO2') +('REF_DW0', '0x80A0', 'DPIO2') +('REF_DW1', '0x80A4', 'DPIO2') +('REF_DW2', '0x80A8', 'DPIO2') +('REF_DW3', '0x80AC', 'DPIO2') +('REF_DW4', '0x80B0', 'DPIO2') +('REF_DW5', '0x80B4', 'DPIO2') +('REF_DW6', '0x80B8', 'DPIO2') +('REF_DW7', '0x80BC', 'DPIO2') +('REF_DW8', '0x80C0', 'DPIO2') +('REF_DW9', '0x80C4', 'DPIO2') +('REF_DW10', '0x80C8', 'DPIO2') +('REF_DW11', '0x80CC', 'DPIO2') +('REF_DW12', '0x80D0', 'DPIO2') +('REF_DW13', '0x80D4', 'DPIO2') +('REF_DW14', '0x80D8', 'DPIO2') +('REF_DW15', '0x80DC', 'DPIO2') +('CL1_DW0', '0x8100', 'DPIO2') +('CL1_DW1', '0x8104', 'DPIO2') +('CL1_DW2', '0x8108', 'DPIO2') +('CL1_DW3', '0x810C', 'DPIO2') +('CL1_DW4', '0x8110', 'DPIO2') +('CL1_DW5', '0x8114', 'DPIO2') +('CL1_DW6', '0x8118', 'DPIO2') +('CL1_DW7', '0x811C', 'DPIO2') +('CL1_DW8', '0x8120', 'DPIO2') +('CL1_DW9', '0x8124', 'DPIO2') +('CL1_DW10', '0x8128', 'DPIO2') +('CL1_DW11', '0x812C', 'DPIO2') +('CL1_DW12', '0x8130', 'DPIO2') +('CL1_DW13', '0x8134', 'DPIO2') +('CL1_DW14', '0x8138', 'DPIO2') +('CL1_DW15', '0x813C', 'DPIO2') +('CL1_DW16', '0x8140', 'DPIO2') +('CL1_DW17', '0x8144', 'DPIO2') +('CL1_DW18', '0x8148', 'DPIO2') +('CL1_DW19', '0x814C', 'DPIO2') +('CL1_DW20', '0x8150', 'DPIO2') +('CL1_DW21', '0x8154', 'DPIO2') +('CL1_DW22', '0x8158', 'DPIO2') +('CL1_DW23', '0x815C', 'DPIO2') +('CL1_DW24', '0x8160', 'DPIO2') +('CL1_DW25', '0x8164', 'DPIO2') +('CL1_DW26', '0x8168', 'DPIO2') +('CL1_DW27', '0x816C', 'DPIO2') +('CL1_DW28', '0x8170', 'DPIO2') +('CL1_DW29', '0x8174', 'DPIO2') +('CL1_DW30', '0x8178', 'DPIO2') +('CL1_DW31', '0x817C', 'DPIO2') +('PLL2_DW0', '0x8180', 'DPIO2') +('PLL2_DW1', '0x8184', 'DPIO2') +('PLL2_DW2', '0x8188', 'DPIO2') +('PLL2_DW3', '0x818C', 'DPIO2') +('PLL2_DW4', '0x8190', 'DPIO2') +('PLL2_DW5', '0x8194', 'DPIO2') +('PLL2_DW6', '0x8198', 'DPIO2') +('PLL2_DW7', '0x819C', 'DPIO2') +('PLL2_DW8', '0x81A0', 'DPIO2') +('PLL2_DW9', '0x81A4', 'DPIO2') +('PLL2_DW10', '0x81A8', 'DPIO2') +('PLL2_DW11', '0x81AC', 'DPIO2') +('PLL2_DW12', '0x81B0', 'DPIO2') +('PLL2_DW13', '0x81B4', 'DPIO2') +('PLL2_DW14', '0x81B8', 'DPIO2') +('PLL2_DW15', '0x81BC', 'DPIO2') +('PLL2_DW16', '0x81C0', 'DPIO2') +('PLL2_DW17', '0x81C4', 'DPIO2') +('PLL2_DW18', '0x81C8', 'DPIO2') +('PLL2_DW19', '0x81CC', 'DPIO2') +('PLL2_DW20', '0x81D0', 'DPIO2') +('PLL2_DW21', '0x81D4', 'DPIO2') +('PLL2_DW22', '0x81D8', 'DPIO2') +('PLL2_DW23', '0x81DC', 'DPIO2') +('PLL2_DW24', '0x81E0', 'DPIO2') +('PLL2_DW25', '0x81E4', 'DPIO2') +('PLL2_DW26', '0x81E8', 'DPIO2') +('PLL2_DW27', '0x81EC', 'DPIO2') +('PLL2_DW28', '0x81F0', 'DPIO2') +('PLL2_DW29', '0x81F4', 'DPIO2') +('PLL2_DW30', '0x81F8', 'DPIO2') +('PLL2_DW31', '0x81FC', 'DPIO2') +('PCS01_CH0_DW0', '0x0200', 'DPIO2') +('PCS01_CH0_DW1', '0x0204', 'DPIO2') +('PCS01_CH0_DW2', '0x0208', 'DPIO2') +('PCS01_CH0_DW3', '0x020C', 'DPIO2') +('PCS01_CH0_DW4', '0x0210', 'DPIO2') +('PCS01_CH0_DW5', '0x0214', 'DPIO2') +('PCS01_CH0_DW6', '0x0218', 'DPIO2') +('PCS01_CH0_DW7', '0x021C', 'DPIO2') +('PCS01_CH0_DW8', '0x0220', 'DPIO2') +('PCS01_CH0_DW9', '0x0224', 'DPIO2') +('PCS01_CH0_DW10', '0x0228', 'DPIO2') +('PCS01_CH0_DW11', '0x022C', 'DPIO2') +('PCS01_CH0_DW12', '0x0230', 'DPIO2') +('PCS01_CH0_DW13', '0x0234', 'DPIO2') +('PCS01_CH0_DW14', '0x0238', 'DPIO2') +('PCS01_CH0_DW15', '0x023C', 'DPIO2') +('PCS01_CH0_DW16', '0x0240', 'DPIO2') +('PCS01_CH0_DW17', '0x0244', 'DPIO2') +('PCS01_CH0_DW18', '0x0248', 'DPIO2') +('PCS01_CH0_DW19', '0x024C', 'DPIO2') +('PCS01_CH0_DW20', '0x0250', 'DPIO2') +('PCS01_CH0_DW21', '0x0254', 'DPIO2') +('PCS01_CH0_DW22', '0x0258', 'DPIO2') +('PCS01_CH0_DW23', '0x025C', 'DPIO2') +('PCS01_CH0_DW24', '0x0260', 'DPIO2') +('PCS01_CH0_DW25', '0x0264', 'DPIO2') +('TX0_CH0_DW0', '0x0080', 'DPIO2') +('TX0_CH0_DW1', '0x0084', 'DPIO2') +('TX0_CH0_DW2', '0x0088', 'DPIO2') +('TX0_CH0_DW3', '0x008C', 'DPIO2') +('TX0_CH0_DW4', '0x0090', 'DPIO2') +('TX0_CH0_DW5', '0x0094', 'DPIO2') +('TX0_CH0_DW6', '0x0098', 'DPIO2') +('TX0_CH0_DW7', '0x009C', 'DPIO2') +('TX0_CH0_DW8', '0x00A0', 'DPIO2') +('TX0_CH0_DW9', '0x00A4', 'DPIO2') +('TX0_CH0_DW10', '0x00A8', 'DPIO2') +('TX0_CH0_DW11', '0x00AC', 'DPIO2') +('TX0_CH0_DW12', '0x00B0', 'DPIO2') +('TX0_CH0_DW13', '0x00B4', 'DPIO2') +('TX0_CH0_DW14', '0x00B8', 'DPIO2') +('TX0_CH0_DW15', '0x00BC', 'DPIO2') +('TX0_CH0_DW16', '0x00C0', 'DPIO2') +('TX0_CH0_DW17', '0x00C4', 'DPIO2') +('TX0_CH0_DW18', '0x00C8', 'DPIO2') +('TX0_CH0_DW19', '0x00CC', 'DPIO2') +('TX0_CH0_DW20', '0x00D0', 'DPIO2') +('TX1_CH0_DW0', '0x0280', 'DPIO2') +('TX1_CH0_DW1', '0x0284', 'DPIO2') +('TX1_CH0_DW2', '0x0288', 'DPIO2') +('TX1_CH0_DW3', '0x028C', 'DPIO2') +('TX1_CH0_DW4', '0x0290', 'DPIO2') +('TX1_CH0_DW5', '0x0294', 'DPIO2') +('TX1_CH0_DW6', '0x0298', 'DPIO2') +('TX1_CH0_DW7', '0x029C', 'DPIO2') +('TX1_CH0_DW8', '0x02A0', 'DPIO2') +('TX1_CH0_DW9', '0x02A4', 'DPIO2') +('TX1_CH0_DW10', '0x02A8', 'DPIO2') +('TX1_CH0_DW11', '0x02AC', 'DPIO2') +('TX1_CH0_DW12', '0x02B0', 'DPIO2') +('TX1_CH0_DW13', '0x02B4', 'DPIO2') +('TX1_CH0_DW14', '0x02B8', 'DPIO2') +('TX1_CH0_DW15', '0x02BC', 'DPIO2') +('TX1_CH0_DW16', '0x02C0', 'DPIO2') +('TX1_CH0_DW17', '0x02C4', 'DPIO2') +('TX1_CH0_DW18', '0x02C8', 'DPIO2') +('TX1_CH0_DW19', '0x02CC', 'DPIO2') +('TX1_CH0_DW20', '0x02D0', 'DPIO2') +('PCS23_CH0_DW0', '0x0400', 'DPIO2') +('PCS23_CH0_DW1', '0x0404', 'DPIO2') +('PCS23_CH0_DW2', '0x0408', 'DPIO2') +('PCS23_CH0_DW3', '0x040C', 'DPIO2') +('PCS23_CH0_DW4', '0x0410', 'DPIO2') +('PCS23_CH0_DW5', '0x0414', 'DPIO2') +('PCS23_CH0_DW6', '0x0418', 'DPIO2') +('PCS23_CH0_DW7', '0x041C', 'DPIO2') +('PCS23_CH0_DW8', '0x0420', 'DPIO2') +('PCS23_CH0_DW9', '0x0424', 'DPIO2') +('PCS23_CH0_DW10', '0x0428', 'DPIO2') +('PCS23_CH0_DW11', '0x042C', 'DPIO2') +('PCS23_CH0_DW12', '0x0430', 'DPIO2') +('PCS23_CH0_DW13', '0x0434', 'DPIO2') +('PCS23_CH0_DW14', '0x0438', 'DPIO2') +('PCS23_CH0_DW15', '0x043C', 'DPIO2') +('PCS23_CH0_DW16', '0x0440', 'DPIO2') +('PCS23_CH0_DW17', '0x0444', 'DPIO2') +('PCS23_CH0_DW18', '0x0448', 'DPIO2') +('PCS23_CH0_DW19', '0x044C', 'DPIO2') +('PCS23_CH0_DW20', '0x0450', 'DPIO2') +('PCS23_CH0_DW21', '0x0454', 'DPIO2') +('PCS23_CH0_DW22', '0x0458', 'DPIO2') +('PCS23_CH0_DW23', '0x045C', 'DPIO2') +('PCS23_CH0_DW24', '0x0460', 'DPIO2') +('PCS23_CH0_DW25', '0x0464', 'DPIO2') +('TX2_CH0_DW0', '0x0480', 'DPIO2') +('TX2_CH0_DW1', '0x0484', 'DPIO2') +('TX2_CH0_DW2', '0x0488', 'DPIO2') +('TX2_CH0_DW3', '0x048C', 'DPIO2') +('TX2_CH0_DW4', '0x0490', 'DPIO2') +('TX2_CH0_DW5', '0x0494', 'DPIO2') +('TX2_CH0_DW6', '0x0498', 'DPIO2') +('TX2_CH0_DW7', '0x049C', 'DPIO2') +('TX2_CH0_DW8', '0x04A0', 'DPIO2') +('TX2_CH0_DW9', '0x04A4', 'DPIO2') +('TX2_CH0_DW10', '0x04A8', 'DPIO2') +('TX2_CH0_DW11', '0x04AC', 'DPIO2') +('TX2_CH0_DW12', '0x04B0', 'DPIO2') +('TX2_CH0_DW13', '0x04B4', 'DPIO2') +('TX2_CH0_DW14', '0x04B8', 'DPIO2') +('TX2_CH0_DW15', '0x04BC', 'DPIO2') +('TX2_CH0_DW16', '0x04C0', 'DPIO2') +('TX2_CH0_DW17', '0x04C4', 'DPIO2') +('TX2_CH0_DW18', '0x04C8', 'DPIO2') +('TX2_CH0_DW19', '0x04CC', 'DPIO2') +('TX2_CH0_DW20', '0x04D0', 'DPIO2') +('TX3_CH0_DW0', '0x0680', 'DPIO2') +('TX3_CH0_DW1', '0x0684', 'DPIO2') +('TX3_CH0_DW2', '0x0688', 'DPIO2') +('TX3_CH0_DW3', '0x068C', 'DPIO2') +('TX3_CH0_DW4', '0x0690', 'DPIO2') +('TX3_CH0_DW5', '0x0694', 'DPIO2') +('TX3_CH0_DW6', '0x0698', 'DPIO2') +('TX3_CH0_DW7', '0x069C', 'DPIO2') +('TX3_CH0_DW8', '0x06A0', 'DPIO2') +('TX3_CH0_DW9', '0x06A4', 'DPIO2') +('TX3_CH0_DW10', '0x06A8', 'DPIO2') +('TX3_CH0_DW11', '0x06AC', 'DPIO2') +('TX3_CH0_DW12', '0x06B0', 'DPIO2') +('TX3_CH0_DW13', '0x06B4', 'DPIO2') +('TX3_CH0_DW14', '0x06B8', 'DPIO2') +('TX3_CH0_DW15', '0x06BC', 'DPIO2') +('TX3_CH0_DW16', '0x06C0', 'DPIO2') +('TX3_CH0_DW17', '0x06C4', 'DPIO2') +('TX3_CH0_DW18', '0x06C8', 'DPIO2') +('TX3_CH0_DW19', '0x06CC', 'DPIO2') +('TX3_CH0_DW20', '0x06D0', 'DPIO2') +('PCS01_CH1_DW0', '0x2600', 'DPIO2') +('PCS01_CH1_DW1', '0x2604', 'DPIO2') +('PCS01_CH1_DW2', '0x2608', 'DPIO2') +('PCS01_CH1_DW3', '0x260C', 'DPIO2') +('PCS01_CH1_DW4', '0x2610', 'DPIO2') +('PCS01_CH1_DW5', '0x2614', 'DPIO2') +('PCS01_CH1_DW6', '0x2618', 'DPIO2') +('PCS01_CH1_DW7', '0x261C', 'DPIO2') +('PCS01_CH1_DW8', '0x2620', 'DPIO2') +('PCS01_CH1_DW9', '0x2624', 'DPIO2') +('PCS01_CH1_DW10', '0x2628', 'DPIO2') +('PCS01_CH1_DW11', '0x262C', 'DPIO2') +('PCS01_CH1_DW12', '0x2630', 'DPIO2') +('PCS01_CH1_DW13', '0x2634', 'DPIO2') +('PCS01_CH1_DW14', '0x2638', 'DPIO2') +('PCS01_CH1_DW15', '0x263C', 'DPIO2') +('PCS01_CH1_DW16', '0x2640', 'DPIO2') +('PCS01_CH1_DW17', '0x2644', 'DPIO2') +('PCS01_CH1_DW18', '0x2648', 'DPIO2') +('PCS01_CH1_DW19', '0x264C', 'DPIO2') +('PCS01_CH1_DW20', '0x2650', 'DPIO2') +('PCS01_CH1_DW21', '0x2654', 'DPIO2') +('PCS01_CH1_DW22', '0x2658', 'DPIO2') +('PCS01_CH1_DW23', '0x265C', 'DPIO2') +('PCS01_CH1_DW24', '0x2660', 'DPIO2') +('PCS01_CH1_DW25', '0x2664', 'DPIO2') +('TX0_CH1_DW0', '0x2480', 'DPIO2') +('TX0_CH1_DW1', '0x2484', 'DPIO2') +('TX0_CH1_DW2', '0x2488', 'DPIO2') +('TX0_CH1_DW3', '0x248C', 'DPIO2') +('TX0_CH1_DW4', '0x2490', 'DPIO2') +('TX0_CH1_DW5', '0x2494', 'DPIO2') +('TX0_CH1_DW6', '0x2498', 'DPIO2') +('TX0_CH1_DW7', '0x249C', 'DPIO2') +('TX0_CH1_DW8', '0x24A0', 'DPIO2') +('TX0_CH1_DW9', '0x24A4', 'DPIO2') +('TX0_CH1_DW10', '0x24A8', 'DPIO2') +('TX0_CH1_DW11', '0x24AC', 'DPIO2') +('TX0_CH1_DW12', '0x24B0', 'DPIO2') +('TX0_CH1_DW13', '0x24B4', 'DPIO2') +('TX0_CH1_DW14', '0x24B8', 'DPIO2') +('TX0_CH1_DW15', '0x24BC', 'DPIO2') +('TX0_CH1_DW16', '0x24C0', 'DPIO2') +('TX0_CH1_DW17', '0x24C4', 'DPIO2') +('TX0_CH1_DW18', '0x24C8', 'DPIO2') +('TX0_CH1_DW19', '0x24CC', 'DPIO2') +('TX0_CH1_DW20', '0x24D0', 'DPIO2') +('TX1_CH1_DW0', '0x2680', 'DPIO2') +('TX1_CH1_DW1', '0x2684', 'DPIO2') +('TX1_CH1_DW2', '0x2688', 'DPIO2') +('TX1_CH1_DW3', '0x268C', 'DPIO2') +('TX1_CH1_DW4', '0x2690', 'DPIO2') +('TX1_CH1_DW5', '0x2694', 'DPIO2') +('TX1_CH1_DW6', '0x2698', 'DPIO2') +('TX1_CH1_DW7', '0x269C', 'DPIO2') +('TX1_CH1_DW8', '0x26A0', 'DPIO2') +('TX1_CH1_DW9', '0x26A4', 'DPIO2') +('TX1_CH1_DW10', '0x26A8', 'DPIO2') +('TX1_CH1_DW11', '0x26AC', 'DPIO2') +('TX1_CH1_DW12', '0x26B0', 'DPIO2') +('TX1_CH1_DW13', '0x26B4', 'DPIO2') +('TX1_CH1_DW14', '0x26B8', 'DPIO2') +('TX1_CH1_DW15', '0x26BC', 'DPIO2') +('TX1_CH1_DW16', '0x26C0', 'DPIO2') +('TX1_CH1_DW17', '0x26C4', 'DPIO2') +('TX1_CH1_DW18', '0x26C8', 'DPIO2') +('TX1_CH1_DW19', '0x26CC', 'DPIO2') +('TX1_CH1_DW20', '0x26D0', 'DPIO2') +('PCS23_CH1_DW0', '0x2800', 'DPIO2') +('PCS23_CH1_DW1', '0x2804', 'DPIO2') +('PCS23_CH1_DW2', '0x2808', 'DPIO2') +('PCS23_CH1_DW3', '0x280C', 'DPIO2') +('PCS23_CH1_DW4', '0x2810', 'DPIO2') +('PCS23_CH1_DW5', '0x2814', 'DPIO2') +('PCS23_CH1_DW6', '0x2818', 'DPIO2') +('PCS23_CH1_DW7', '0x281C', 'DPIO2') +('PCS23_CH1_DW8', '0x2820', 'DPIO2') +('PCS23_CH1_DW9', '0x2824', 'DPIO2') +('PCS23_CH1_DW10', '0x2828', 'DPIO2') +('PCS23_CH1_DW11', '0x282C', 'DPIO2') +('PCS23_CH1_DW12', '0x2830', 'DPIO2') +('PCS23_CH1_DW13', '0x2834', 'DPIO2') +('PCS23_CH1_DW14', '0x2838', 'DPIO2') +('PCS23_CH1_DW15', '0x283C', 'DPIO2') +('PCS23_CH1_DW16', '0x2840', 'DPIO2') +('PCS23_CH1_DW17', '0x2844', 'DPIO2') +('PCS23_CH1_DW18', '0x2848', 'DPIO2') +('PCS23_CH1_DW19', '0x284C', 'DPIO2') +('PCS23_CH1_DW20', '0x2850', 'DPIO2') +('PCS23_CH1_DW21', '0x2854', 'DPIO2') +('PCS23_CH1_DW22', '0x2858', 'DPIO2') +('PCS23_CH1_DW23', '0x285C', 'DPIO2') +('PCS23_CH1_DW24', '0x2860', 'DPIO2') +('PCS23_CH1_DW25', '0x2864', 'DPIO2') +('TX2_CH1_DW0', '0x2880', 'DPIO2') +('TX2_CH1_DW1', '0x2884', 'DPIO2') +('TX2_CH1_DW2', '0x2888', 'DPIO2') +('TX2_CH1_DW3', '0x288C', 'DPIO2') +('TX2_CH1_DW4', '0x2890', 'DPIO2') +('TX2_CH1_DW5', '0x2894', 'DPIO2') +('TX2_CH1_DW6', '0x2898', 'DPIO2') +('TX2_CH1_DW7', '0x289C', 'DPIO2') +('TX2_CH1_DW8', '0x28A0', 'DPIO2') +('TX2_CH1_DW9', '0x28A4', 'DPIO2') +('TX2_CH1_DW10', '0x28A8', 'DPIO2') +('TX2_CH1_DW11', '0x28AC', 'DPIO2') +('TX2_CH1_DW12', '0x28B0', 'DPIO2') +('TX2_CH1_DW13', '0x28B4', 'DPIO2') +('TX2_CH1_DW14', '0x28B8', 'DPIO2') +('TX2_CH1_DW15', '0x28BC', 'DPIO2') +('TX2_CH1_DW16', '0x28C0', 'DPIO2') +('TX2_CH1_DW17', '0x28C4', 'DPIO2') +('TX2_CH1_DW18', '0x28C8', 'DPIO2') +('TX2_CH1_DW19', '0x28CC', 'DPIO2') +('TX2_CH1_DW20', '0x28D0', 'DPIO2') +('TX3_CH1_DW0', '0x2A80', 'DPIO2') +('TX3_CH1_DW1', '0x2A84', 'DPIO2') +('TX3_CH1_DW2', '0x2A88', 'DPIO2') +('TX3_CH1_DW3', '0x2A8C', 'DPIO2') +('TX3_CH1_DW4', '0x2A90', 'DPIO2') +('TX3_CH1_DW5', '0x2A94', 'DPIO2') +('TX3_CH1_DW6', '0x2A98', 'DPIO2') +('TX3_CH1_DW7', '0x2A9C', 'DPIO2') +('TX3_CH1_DW8', '0x2AA0', 'DPIO2') +('TX3_CH1_DW9', '0x2AA4', 'DPIO2') +('TX3_CH1_DW10', '0x2AA8', 'DPIO2') +('TX3_CH1_DW11', '0x2AAC', 'DPIO2') +('TX3_CH1_DW12', '0x2AB0', 'DPIO2') +('TX3_CH1_DW13', '0x2AB4', 'DPIO2') +('TX3_CH1_DW14', '0x2AB8', 'DPIO2') +('TX3_CH1_DW15', '0x2ABC', 'DPIO2') +('TX3_CH1_DW16', '0x2AC0', 'DPIO2') +('TX3_CH1_DW17', '0x2AC4', 'DPIO2') +('TX3_CH1_DW18', '0x2AC8', 'DPIO2') +('TX3_CH1_DW19', '0x2ACC', 'DPIO2') +('TX3_CH1_DW20', '0x2AD0', 'DPIO2') diff --git a/tools/registers/chv_pipe_c.txt b/tools/registers/chv_pipe_c.txt new file mode 100644 index 00000000..8c5d3f87 --- /dev/null +++ b/tools/registers/chv_pipe_c.txt @@ -0,0 +1,168 @@ +('PIPEC_DSL', '0x74000', '0x180000') +('PIPEC_SLC', '0x74004', '0x180000') +('PIPECCONF', '0x74008', '0x180000') +('PIPECGCMAXRED', '0x74010', '0x180000') +('PIPECGCMAXGREEN', '0x74014', '0x180000') +('PIPECGCMAXBLUE', '0x74018', '0x180000') +('PIPECSTAT', '0x74024', '0x180000') +('PIPECFRAMECOUNT', '0x74040', '0x180000') +('PIPECFLIPCOUNT', '0x74044', '0x180000') +('PIPECMSAMISC', '0x74048', '0x180000') + +('DSPCADDR', '0x7417C', '0x180000') +('DSPCCNTR', '0x74180', '0x180000') +('DSPCLINOFF', '0x74184', '0x180000') +('DSPCSTRIDE', '0x74188', '0x180000') +('DSPCKEYVAL', '0x74194', '0x180000') +('DSPCKEYMSK', '0x74198', '0x180000') +('DSPCSURF', '0x7419C', '0x180000') +('DSPCTILEOFF', '0x741A4', '0x180000') +('DSPCSURFLIVE', '0x741AC', '0x180000') +('DSPCFLPQSTAT', '0x74200', '0x180000') + +('CURCCNTR', '0x700E0', '0x180000') +('CURCBASE', '0x700E4', '0x180000') +('CURCPOS', '0x700E8', '0x180000') +('CURCRESV', '0x700EC', '0x180000') +('CURCPALET0', '0x700F0', '0x180000') +('CURCPALET1', '0x700F4', '0x180000') +('CURCPALET2', '0x700F8', '0x180000') +('CURCPALET3', '0x700FC', '0x180000') +('CURCLIVEBASE', '0x700B0', '0x180000') + +('SPECNTR', '0x72580', '0x180000') +('SPELINOFF', '0x72584', '0x180000') +('SPESTRIDE', '0x72588', '0x180000') +('SPEPOS', '0x7258C', '0x180000') +('SPESIZE', '0x72590', '0x180000') +('SPEKEYMINVAL', '0x72594', '0x180000') +('SPEKEYMSK', '0x72598', '0x180000') +('SPESURF', '0x7259C', '0x180000') +('SPEKEYMAXVAL', '0x725A0', '0x180000') +('SPETILEOFF', '0x725A4', '0x180000') +('SPECONTALPHA', '0x725A8', '0x180000') +('SPELIVESURF', '0x725AC', '0x180000') +('SPECLRC0', '0x725D0', '0x180000') +('SPECLRC1', '0x725D4', '0x180000') +('SPEGAMC5', '0x725E0', '0x180000') +('SPEGAMC4', '0x725E4', '0x180000') +('SPEGAMC3', '0x725E8', '0x180000') +('SPEGAMC2', '0x725EC', '0x180000') +('SPEGAMC1', '0x725F0', '0x180000') +('SPEGAMC0', '0x725F4', '0x180000') + +('SPFCNTR', '0x72680', '0x180000') +('SPFLINOFF', '0x72684', '0x180000') +('SPFSTRIDE', '0x72688', '0x180000') +('SPFPOS', '0x7268C', '0x180000') +('SPFSIZE', '0x72690', '0x180000') +('SPFKEYMINVAL', '0x72694', '0x180000') +('SPFKEYMSK', '0x72698', '0x180000') +('SPFSURF', '0x7269C', '0x180000') +('SPFKEYMAXVAL', '0x726A0', '0x180000') +('SPFTILEOFF', '0x726A4', '0x180000') +('SPFCONTALPHA', '0x726A8', '0x180000') +('SPFLIVESURF', '0x726AC', '0x180000') +('SPFCLRC0', '0x726D0', '0x180000') +('SPFCLRC1', '0x726D4', '0x180000') +('SPFGAMC5', '0x726E0', '0x180000') +('SPFGAMC4', '0x726E4', '0x180000') +('SPFGAMC3', '0x726E8', '0x180000') +('SPFGAMC2', '0x726EC', '0x180000') +('SPFGAMC1', '0x726F0', '0x180000') +('SPFGAMC0', '0x726F4', '0x180000') + +('DPALETTE_C', '0xC000', '0x180000') +('DPLLC_CTRL', '0x6030', '0x180000') +('DPLLCMD', '0x603C', '0x180000') + +('HTOTAL_C', '0x63000', '0x180000') +('HBLANK_C', '0x63004', '0x180000') +('HSYNC_C', '0x63008', '0x180000') +('VTOTAL_C', '0x6300C', '0x180000') +('VBLANK_C', '0x63010', '0x180000') +('VSYNC_C', '0x63014', '0x180000') +('PIPECSRC', '0x6301C', '0x180000') +('BCLRPAT_C', '0x63020', '0x180000') +('VSYNCSHIFT_C', '0x63028', '0x180000') + +('TRANSC_DATA_M1', '0x63030', '0x180000') +('TRANSC_DATA_N1', '0x63034', '0x180000') +('TRANSC_DATA_M2', '0x63038', '0x180000') +('TRANSC_DATA_N2', '0x6303C', '0x180000') +('TRANSC_LINK_M1', '0x63040', '0x180000') +('TRANSC_LINK_N1', '0x63044', '0x180000') +('TRANSC_LINK_M2', '0x63048', '0x180000') +('TRANSC_LINK_N2', '0x6304C', '0x180000') + +('CRC_CTRL_RED_C', '0x63050', '0x180000') +('CRC_CTRL_GREEN_C', '0x63054', '0x180000') +('CRC_CTRL_BLUE_C', '0x63058', '0x180000') +('CRC_CTRL_ALPHA_C', '0x6305C', '0x180000') +('CRC_CTRL_RESIDUE2_C', '0x63070', '0x180000') +('CRC_RES_RED_C', '0x63060', '0x180000') +('CRC_RES_GREEN_C', '0x63064', '0x180000') +('CRC_RES_BLUE_C', '0x63068', '0x180000') +('CRC_RES_ALPHA_C', '0x6306C', '0x180000') +('CRC_RES_RESIDUAL2_C', '0x63080', '0x180000') + +('PSRCTLC', '0x63090', '0x180000') +('PSRSTATC', '0x63094', '0x180000') +('PSRCRC1C', '0x63098', '0x180000') +('PSRCRC2C', '0x6309C', '0x180000') +('VSCSDPC', '0x630A0', '0x180000') + +('PIPEC_WGCC_C01_C00', '0x630B0', '0x180000') +('PIPEC_WGCC_C02', '0x630B4', '0x180000') +('PIPEC_WGCC_C11_C10', '0x630B8', '0x180000') +('PIPEC_WGCC_C12', '0x630BC', '0x180000') +('PIPEC_WGCC_C21_C20', '0x630C0', '0x180000') +('PIPEC_WGCC_C22', '0x630C4', '0x180000') + +('VIDEO_DIP_CTL_C', '0x611F0', '0x180000') +('VIDEO_DIP_DATA_C', '0x611F4', '0x180000') +('VIDEO_DIP_GDCP_PAYLOAD_C', '0x611F8', '0x180000') + +('PIPEC_CGM_DEGAMMA', '0x6A000', '0x180000') +('PIPEC_CGM_GAMMA', '0x6B000', '0x180000') +('PIPEC_CGM_CSC_COEFF01', '0x6B900', '0x180000') +('PIPEC_CGM_CSC_COEFF23', '0x6B904', '0x180000') +('PIPEC_CGM_CSC_COEFF45', '0x6B908', '0x180000') +('PIPEC_CGM_CSC_COEFF67', '0x6B90C', '0x180000') +('PIPEC_CGM_CSC_COEFF8', '0x6B910', '0x180000') +('PIPEC_CGM_CONTROL', '0x6BA00', '0x180000') + +('PIPEC_PP_STATUS', '0x61900', '0x180000') +('PIPEC_PP_CONTROL', '0x61904', '0x180000') +('PIPEC_PP_ON_DELAYS', '0x61908', '0x180000') +('PIPEC_PP_OFF_DELAYS', '0x6190C', '0x180000') +('PIPEC_PP_DIVISOR', '0x61910', '0x180000') + +('AUD_CONFIG_C', '0x62200', '0x180000') +('AUD_MISC_CTRL_C', '0x62210', '0x180000') +('AUD_CTS_ENABLE_C', '0x62228', '0x180000') +('AUD_HDMIW_HDMIEDID_C', '0x62250', '0x180000') +('AUD_HDMIW_INFOFR_C', '0x62254', '0x180000') +('AUD_OUT_DIG_CNVT_C', '0x62280', '0x180000') +('AUD_OUT_STR_DESC_C', '0x62284', '0x180000') +('AUD_CNTL_ST_C', '0x622B4', '0x180000') +('AUD_OUT_DIG_CNVTC_DBG', '0x62F48', '0x180000') + +('STREAM_C_LPE_AUD_CONFIG', '0x65900', '0x180000') +('STREAM_C_LPE_AUD_CH_STATUS_0', '0x65908', '0x180000') +('STREAM_C_LPE_AUD_CH_STATUS_1', '0x6590C', '0x180000') +('STREAM_C_LPE_AUD_HDMI_CTS_DP_MAUD', '0x65910', '0x180000') +('STREAM_C_LPE_AUD_HDMI_N_DP_NAUD', '0x65914', '0x180000') +('STREAM_C_LPE_AUD_BUFFER_CONFIG', '0x65920', '0x180000') +('STREAM_C_LPE_AUD_BUF_CH_SWP', '0x65924', '0x180000') +('STREAM_C_LPE_AUD_BUF_A_ADDR', '0x65940', '0x180000') +('STREAM_C_LPE_AUD_BUF_A_LENGTH', '0x65944', '0x180000') +('STREAM_C_LPE_AUD_BUF_B_ADDR', '0x65948', '0x180000') +('STREAM_C_LPE_AUD_BUF_B_LENGTH', '0x6594C', '0x180000') +('STREAM_C_LPE_AUD_BUF_C_ADDR', '0x65950', '0x180000') +('STREAM_C_LPE_AUD_BUF_C_LENGTH', '0x65954', '0x180000') +('STREAM_C_LPE_AUD_BUF_D_ADDR', '0x65958', '0x180000') +('STREAM_C_LPE_AUD_BUF_D_LENGTH', '0x6595C', '0x180000') +('STREAM_C_LPE_AUD_CNTL_ST', '0x65960', '0x180000') +('STREAM_C_LPE_AUD_HDMI_STATUS', '0x65964', '0x180000') +('STREAM_C_LPE_AUD_HDMIW_INFOFR', '0x65968', '0x180000') diff --git a/tools/registers/common_display.txt b/tools/registers/common_display.txt new file mode 100644 index 00000000..8bead7f8 --- /dev/null +++ b/tools/registers/common_display.txt @@ -0,0 +1,197 @@ +('CPU_VGACNTRL', '0x00041000', '') +('PORT_DBG', '0x00042308', '') +('DIGITAL_PORT_HOTPLUG_CNTRL', '0x00044030', '') +('FDI_PLL_BIOS_0', '0x00046000', '') +('FDI_PLL_BIOS_1', '0x00046004', '') +('FDI_PLL_BIOS_2', '0x00046008', '') +('DISPLAY_PORT_PLL_BIOS_0', '0x0004600c', '') +('DISPLAY_PORT_PLL_BIOS_1', '0x00046010', '') +('DISPLAY_PORT_PLL_BIOS_2', '0x00046014', '') +('FDI_PLL_FREQ_CTL', '0x00046030', '') +('BLC_PWM_CPU_CTL2', '0x00048250', '') +('BLC_PWM_CPU_CTL', '0x00048254', '') +('HTOTAL_A', '0x00060000', '') +('HBLANK_A', '0x00060004', '') +('HSYNC_A', '0x00060008', '') +('VTOTAL_A', '0x0006000c', '') +('VBLANK_A', '0x00060010', '') +('VSYNC_A', '0x00060014', '') +('PIPEASRC', '0x0006001c', '') +('VSYNCSHIFT_A', '0x00060028', '') +('PIPEA_DATA_M1', '0x00060030', '') +('PIPEA_DATA_N1', '0x00060034', '') +('PIPEA_DATA_M2', '0x00060038', '') +('PIPEA_DATA_N2', '0x0006003c', '') +('PIPEA_LINK_M1', '0x00060040', '') +('PIPEA_LINK_N1', '0x00060044', '') +('PIPEA_LINK_M2', '0x00060048', '') +('PIPEA_LINK_N2', '0x0006004c', '') +('FDI_TXA_CTL', '0x00060100', '') +('HTOTAL_B', '0x00061000', '') +('HBLANK_B', '0x00061004', '') +('HSYNC_B', '0x00061008', '') +('VTOTAL_B', '0x0006100c', '') +('VBLANK_B', '0x00061010', '') +('VSYNC_B', '0x00061014', '') +('PIPEBSRC', '0x0006101c', '') +('VSYNCSHIFT_B', '0x00061028', '') +('PIPEB_DATA_M1', '0x00061030', '') +('PIPEB_DATA_N1', '0x00061034', '') +('PIPEB_DATA_M2', '0x00061038', '') +('PIPEB_DATA_N2', '0x0006103c', '') +('PIPEB_LINK_M1', '0x00061040', '') +('PIPEB_LINK_N1', '0x00061044', '') +('PIPEB_LINK_M2', '0x00061048', '') +('PIPEB_LINK_N2', '0x0006104c', '') +('FDI_TXB_CTL', '0x00061100', '') +('HTOTAL_C', '0x00062000', '') +('HBLANK_C', '0x00062004', '') +('HSYNC_C', '0x00062008', '') +('VTOTAL_C', '0x0006200c', '') +('VBLANK_C', '0x00062010', '') +('VSYNC_C', '0x00062014', '') +('PIPECSRC', '0x0006201c', '') +('VSYNCSHIFT_C', '0x00062028', '') +('PIPEC_DATA_M1', '0x00062030', '') +('PIPEC_DATA_N1', '0x00062034', '') +('PIPEC_DATA_M2', '0x00062038', '') +('PIPEC_DATA_N2', '0x0006203c', '') +('PIPEC_LINK_M1', '0x00062040', '') +('PIPEC_LINK_N1', '0x00062044', '') +('PIPEC_LINK_M2', '0x00062048', '') +('PIPEC_LINK_N2', '0x0006204c', '') +('FDI_TXC_CTL', '0x00062100', '') +('CPU_eDP_A', '0x00064000', '') +('PFA_WIN_POS', '0x00068070', '') +('PFA_WIN_SIZE', '0x00068074', '') +('PFA_CTL_1', '0x00068080', '') +('PFA_CTL_2', '0x00068084', '') +('PFA_CTL_3', '0x00068088', '') +('PFA_CTL_4', '0x00068090', '') +('PFB_WIN_POS', '0x00068870', '') +('PFB_WIN_SIZE', '0x00068874', '') +('PFB_CTL_1', '0x00068880', '') +('PFB_CTL_2', '0x00068884', '') +('PFB_CTL_3', '0x00068888', '') +('PFB_CTL_4', '0x00068890', '') +('PFC_WIN_POS', '0x00069070', '') +('PFC_WIN_SIZE', '0x00069074', '') +('PFC_CTL_1', '0x00069080', '') +('PFC_CTL_2', '0x00069084', '') +('PFC_CTL_3', '0x00069088', '') +('PFC_CTL_4', '0x00069090', '') +('PIPEACONF', '0x00070008', '') +('DSPACNTR', '0x00070180', '') +('DSPABASE', '0x00070184', '') +('DSPASTRIDE', '0x00070188', '') +('DSPASURF', '0x0007019c', '') +('DSPATILEOFF', '0x000701a4', '') +('PIPEBCONF', '0x00071008', '') +('DSPBCNTR', '0x00071180', '') +('DSPBBASE', '0x00071184', '') +('DSPBSTRIDE', '0x00071188', '') +('DSPBSURF', '0x0007119c', '') +('DSPBTILEOFF', '0x000711a4', '') +('PIPECCONF', '0x00072008', '') +('DSPCCNTR', '0x00072180', '') +('DSPCBASE', '0x00072184', '') +('DSPCSTRIDE', '0x00072188', '') +('DSPCSURF', '0x0007219c', '') +('DSPCTILEOFF', '0x000721a4', '') +('PCH_DPLL_A', '0x000c6014', '') +('PCH_DPLL_B', '0x000c6018', '') +('PCH_FPA0', '0x000c6040', '') +('PCH_FPA1', '0x000c6044', '') +('PCH_FPB0', '0x000c6048', '') +('PCH_FPB1', '0x000c604c', '') +('PCH_DREF_CONTROL', '0x000c6200', '') +('PCH_RAWCLK_FREQ', '0x000c6204', '') +('PCH_DPLL_TMR_CFG', '0x000c6208', '') +('PCH_SSC4_PARMS', '0x000c6210', '') +('PCH_SSC4_AUX_PARMS', '0x000c6214', '') +('PCH_DPLL_ANALOG_CTL', '0x000c6300', '') +('PCH_DPLL_SEL', '0x000c7000', '') +('PCH_PP_STATUS', '0x000c7200', '') +('PCH_PP_CONTROL', '0x000c7204', '') +('PCH_PP_ON_DELAYS', '0x000c7208', '') +('PCH_PP_OFF_DELAYS', '0x000c720c', '') +('PCH_PP_DIVISOR', '0x000c7210', '') +('BLC_PWM_PCH_CTL1', '0x000c8250', '') +('BLC_PWM_PCH_CTL2', '0x000c8254', '') +('TRANS_HTOTAL_A', '0x000e0000', '') +('TRANS_HBLANK_A', '0x000e0004', '') +('TRANS_HSYNC_A', '0x000e0008', '') +('TRANS_VTOTAL_A', '0x000e000c', '') +('TRANS_VBLANK_A', '0x000e0010', '') +('TRANS_VSYNC_A', '0x000e0014', '') +('TRANS_VSYNCSHIFT_A', '0x000e0028', '') +('TRANSA_DATA_M1', '0x000e0030', '') +('TRANSA_DATA_N1', '0x000e0034', '') +('TRANSA_DATA_M2', '0x000e0038', '') +('TRANSA_DATA_N2', '0x000e003c', '') +('TRANSA_DP_LINK_M1', '0x000e0040', '') +('TRANSA_DP_LINK_N1', '0x000e0044', '') +('TRANSA_DP_LINK_M2', '0x000e0048', '') +('TRANSA_DP_LINK_N2', '0x000e004c', '') +('TRANS_DP_CTL_A', '0x000e0300', '') +('TRANS_HTOTAL_B', '0x000e1000', '') +('TRANS_HBLANK_B', '0x000e1004', '') +('TRANS_HSYNC_B', '0x000e1008', '') +('TRANS_VTOTAL_B', '0x000e100c', '') +('TRANS_VBLANK_B', '0x000e1010', '') +('TRANS_VSYNC_B', '0x000e1014', '') +('TRANS_VSYNCSHIFT_B', '0x000e1028', '') +('TRANSB_DATA_M1', '0x000e1030', '') +('TRANSB_DATA_N1', '0x000e1034', '') +('TRANSB_DATA_M2', '0x000e1038', '') +('TRANSB_DATA_N2', '0x000e103c', '') +('TRANSB_DP_LINK_M1', '0x000e1040', '') +('TRANSB_DP_LINK_N1', '0x000e1044', '') +('TRANSB_DP_LINK_M2', '0x000e1048', '') +('TRANSB_DP_LINK_N2', '0x000e104c', '') +('PCH_ADPA', '0x000e1100', '') +('HDMIB', '0x000e1140', '') +('HDMIC', '0x000e1150', '') +('HDMID', '0x000e1160', '') +('PCH_LVDS', '0x000e1180', '') +('TRANS_DP_CTL_B', '0x000e1300', '') +('TRANS_HTOTAL_C', '0x000e2000', '') +('TRANS_HBLANK_C', '0x000e2004', '') +('TRANS_HSYNC_C', '0x000e2008', '') +('TRANS_VTOTAL_C', '0x000e200c', '') +('TRANS_VBLANK_C', '0x000e2010', '') +('TRANS_VSYNC_C', '0x000e2014', '') +('TRANS_VSYNCSHIFT_C', '0x000e2028', '') +('TRANSC_DATA_M1', '0x000e2030', '') +('TRANSC_DATA_N1', '0x000e2034', '') +('TRANSC_DATA_M2', '0x000e2038', '') +('TRANSC_DATA_N2', '0x000e203c', '') +('TRANSC_DP_LINK_M1', '0x000e2040', '') +('TRANSC_DP_LINK_N1', '0x000e2044', '') +('TRANSC_DP_LINK_M2', '0x000e2048', '') +('TRANSC_DP_LINK_N2', '0x000e204c', '') +('TRANS_DP_CTL_C', '0x000e2300', '') +('PCH_DP_B', '0x000e4100', '') +('PCH_DP_C', '0x000e4200', '') +('PCH_DP_D', '0x000e4300', '') +('TRANSACONF', '0x000f0008', '') +('FDI_RXA_CTL', '0x000f000c', '') +('FDI_RXA_MISC', '0x000f0010', '') +('FDI_RXA_IIR', '0x000f0014', '') +('FDI_RXA_IMR', '0x000f0018', '') +('FDI_RXA_TUSIZE1', '0x000f0030', '') +('FDI_RXA_TUSIZE2', '0x000f0038', '') +('TRANSBCONF', '0x000f1008', '') +('FDI_RXB_CTL', '0x000f100c', '') +('FDI_RXB_MISC', '0x000f1010', '') +('FDI_RXB_IIR', '0x000f1014', '') +('FDI_RXB_IMR', '0x000f1018', '') +('FDI_RXB_TUSIZE1', '0x000f1030', '') +('FDI_RXB_TUSIZE2', '0x000f1038', '') +('TRANSCCONF', '0x000f2008', '') +('FDI_RXC_CTL', '0x000f200c', '') +('FDI_RXC_MISC', '0x000f2010', '') +('FDI_RXC_TUSIZE1', '0x000f2030', '') +('FDI_RXC_TUSIZE2', '0x000f2038', '') +('FDI_PLL_CTL_1', '0x000fe000', '') +('FDI_PLL_CTL_2', '0x000fe004', '') diff --git a/tools/registers/gen6_other.txt b/tools/registers/gen6_other.txt new file mode 100644 index 00000000..9aa65390 --- /dev/null +++ b/tools/registers/gen6_other.txt @@ -0,0 +1 @@ +('GFX_MODE', '0x00002520', '') diff --git a/tools/registers/gen7_other.txt b/tools/registers/gen7_other.txt new file mode 100644 index 00000000..9db9b4e2 --- /dev/null +++ b/tools/registers/gen7_other.txt @@ -0,0 +1,3 @@ +('RCS_MODE_GEN7', '0x0000229c', '') +('VCS_MODE_GEN7', '0x0001229c', '') +('BCS_MODE_GEN7', '0x0002229c', '') diff --git a/tools/registers/gen8_interrupt.txt b/tools/registers/gen8_interrupt.txt new file mode 100644 index 00000000..d3966488 --- /dev/null +++ b/tools/registers/gen8_interrupt.txt @@ -0,0 +1,44 @@ +('GEN8_MASTER_IRQ', '0x00044200', '') +('GEN8_GT_ISR0', '0x00044300', '') +('GEN8_GT_IMR0', '0x00044304', '') +('GEN8_GT_IIR0', '0x00044308', '') +('GEN8_GT_IER0', '0x0004430c', '') +('GEN8_GT_ISR1', '0x00044310', '') +('GEN8_GT_IMR1', '0x00044314', '') +('GEN8_GT_IIR1', '0x00044318', '') +('GEN8_GT_IER1', '0x0004431c', '') +('GEN8_GT_ISR2', '0x00044320', '') +('GEN8_GT_IMR2', '0x00044324', '') +('GEN8_GT_IIR2', '0x00044328', '') +('GEN8_GT_IER2', '0x0004432c', '') +('GEN8_GT_ISR3', '0x00044330', '') +('GEN8_GT_IMR3', '0x00044334', '') +('GEN8_GT_IIR3', '0x00044338', '') +('GEN8_GT_IER3', '0x0004433c', '') +('GEN8_DE_PIPE_ISR0', '0x44400', '') +('GEN8_DE_PIPE_IMR0', '0x44404', '') +('GEN8_DE_PIPE_IIR0', '0x44408', '') +('GEN8_DE_PIPE_IER0', '0x4440c', '') +('GEN8_DE_PIPE_ISR1', '0x44410', '') +('GEN8_DE_PIPE_IMR1', '0x44414', '') +('GEN8_DE_PIPE_IIR1', '0x44418', '') +('GEN8_DE_PIPE_IER1', '0x4441c', '') +('GEN8_DE_PIPE_ISR2', '0x44420', '') +('GEN8_DE_PIPE_IMR2', '0x44424', '') +('GEN8_DE_PIPE_IIR2', '0x44428', '') +('GEN8_DE_PIPE_IER2', '0x4442c', '') +('GEN8_DE_PORT_ISR', '0x44440', '') +('GEN8_DE_PORT_IMR', '0x44444', '') +('GEN8_DE_PORT_IIR', '0x44448', '') +('GEN8_DE_PORT_IER', '0x4444c', '') +('GEN8_DE_MISC_ISR', '0x44460', '') +('GEN8_DE_MISC_IMR', '0x44464', '') +('GEN8_DE_MISC_IIR', '0x44468', '') +('GEN8_DE_MISC_IER', '0x4446c', '') +('GEN8_PCU_ISR', '0x444e0', '') +('GEN8_PCU_IMR', '0x444e4', '') +('GEN8_PCU_IIR', '0x444e8', '') +('GEN8_PCU_IER', '0x444ec', '') +('RENDER_IMR', '0x000020a8', '') +('BSD_IMR', '0x000120a8', '') +('BLT_IMR', '0x000220a8', '') diff --git a/tools/registers/gen8_other.txt b/tools/registers/gen8_other.txt new file mode 100644 index 00000000..02c6f096 --- /dev/null +++ b/tools/registers/gen8_other.txt @@ -0,0 +1,2 @@ +('PRIVATE_PAT1', '0x000040e0', '') +('PRIVATE_PAT2', '0x000040e4', '') diff --git a/tools/registers/haswell b/tools/registers/haswell new file mode 100644 index 00000000..94ffb7c7 --- /dev/null +++ b/tools/registers/haswell @@ -0,0 +1,5 @@ +common_display.txt +gen7_other.txt +haswell_other.txt +audio_config_haswell_plus.txt +audio_debug_haswell_plus.txt diff --git a/tools/registers/haswell_other.txt b/tools/registers/haswell_other.txt new file mode 100644 index 00000000..4529aabe --- /dev/null +++ b/tools/registers/haswell_other.txt @@ -0,0 +1,25 @@ +('VECS_MODE_GEN7', '0x0001a29c', '') + +('HSW_FUSE_STRAP', '0x00042014', '') +('HSW_PWR_WELL_BIOS', '0x00045400', '') +('HSW_PWR_WELL_DRIVER', '0x00045404', '') +('HSW_PWR_WELL_KVMR', '0x00045408', '') +('HSW_PWR_WELL_DEBUG', '0x0004540c', '') +('HSW_PWR_WELL_CTL5', '0x00045410', '') +('HSW_PWR_WELL_CTL6', '0x00045414', '') + +# Watermarks +('WM_PIPE_A', '0x45100', '') +('WM_LINETIME_A', '0x45270', '') +('WM_PIPE_B', '0x45104', '') +('WM_LINETIME_B', '0x45274', '') +('WM_PIPE_C', '0x45200', '') +('WM_LINETIME_C', '0x45278', '') +('WM_LP_1', '0x45108', '') +('WM_LP_2', '0x4510c', '') +('WM_LP_3', '0x45110', '') +('WM_LP_SPR_1', '0x45120', '') +('WM_LP_SPR_2', '0x45124', '') +('WM_LP_SPR_3', '0x45128', '') +('WM_MISC', '0x45260', '') +('WM_DBG', '0x45280', '') diff --git a/tools/registers/ivybridge b/tools/registers/ivybridge new file mode 100644 index 00000000..79bda9b1 --- /dev/null +++ b/tools/registers/ivybridge @@ -0,0 +1,2 @@ +common_display.txt +gen7_other.txt diff --git a/tools/registers/sandybridge b/tools/registers/sandybridge new file mode 100644 index 00000000..a0a4474a --- /dev/null +++ b/tools/registers/sandybridge @@ -0,0 +1,2 @@ +common_display.txt +gen6_other.txt diff --git a/tools/registers/skl_display.txt b/tools/registers/skl_display.txt new file mode 100644 index 00000000..d995e3a6 --- /dev/null +++ b/tools/registers/skl_display.txt @@ -0,0 +1,400 @@ +# CLOCKS +('DPLL_STATUS', '0x6c060', '') +('DPLL1_CFGCR1', '0x6c040', '') +('DPLL2_CFGCR1', '0x6c048', '') +('DPLL3_CFGCR1', '0x6c050', '') +('DPLL1_CFGCR2', '0x6c044', '') +('DPLL2_CFGCR2', '0x6c04c', '') +('DPLL3_CFGCR2', '0x6c054', '') +('DPLL_CTRL1', '0x6c058', '') +('DPLL_CTRL2', '0x6c05c', '') +('CDCLK_CTL', '0x46000', '') +('LCPLL1_CTL', '0x46010', '') +('LCPLL2_CTL', '0x46014', '') +('TRANS_CLK_SEL_A', '0x46140', '') +('TRANS_CLK_SEL_B', '0x46144', '') +('TRANS_CLK_SEL_C', '0x46148', '') +('WRPLL_CTL1', '0x46040', '') +('WRPLL_CTL2', '0x46060', '') +# PIPE_A_PLANE +('PLANE_BUF_CFG_1_A', '0x7027c', '') +('PLANE_BUF_CFG_2_A', '0x7037c', '') +('PLANE_BUF_CFG_3_A', '0x7047c', '') +('PLANE_NV12_BUF_CFG_1_A', '0x70278', '') +('PLANE_NV12_BUF_CFG_2_A', '0x70378', '') +('PLANE_NV12_BUF_CFG_3_A', '0x70478', '') +('PLANE_CTL_1_A', '0x70180', '') +('PLANE_CTL_2_A', '0x70280', '') +('PLANE_CTL_3_A', '0x70380', '') +('PLANE_KEYMAX_1_A', '0x701a0', '') +('PLANE_KEYMAX_2_A', '0x702a0', '') +('PLANE_KEYMAX_3_A', '0x703a0', '') +('PLANE_KEYMSK_1_A', '0x70198', '') +('PLANE_KEYMSK_2_A', '0x70298', '') +('PLANE_KEYMSK_3_A', '0x70398', '') +('PLANE_KEYVAL_1_A', '0x70194', '') +('PLANE_KEYVAL_2_A', '0x70294', '') +('PLANE_KEYVAL_3_A', '0x70394', '') +('PLANE_OFFSET_1_A', '0x701a4', '') +('PLANE_OFFSET_2_A', '0x702a4', '') +('PLANE_OFFSET_3_A', '0x703a4', '') +('PLANE_AUX_OFFSET_1_A', '0x701c4', '') +('PLANE_AUX_OFFSET_2_A', '0x702c4', '') +('PLANE_AUX_OFFSET_3_A', '0x703c4', '') +('PLANE_POS_1_A', '0x7018c', '') +('PLANE_POS_2_A', '0x7028c', '') +('PLANE_POS_3_A', '0x7038c', '') +('PLANE_SIZE_1_A', '0x70190', '') +('PLANE_SIZE_2_A', '0x70290', '') +('PLANE_SIZE_3_A', '0x70390', '') +('PLANE_STRIDE_1_A', '0x70188', '') +('PLANE_STRIDE_2_A', '0x70288', '') +('PLANE_STRIDE_3_A', '0x70388', '') +('PLANE_SURF_1_A', '0x7019c', '') +('PLANE_SURF_2_A', '0x7029c', '') +('PLANE_SURF_3_A', '0x7039c', '') +('PLANE_SURFLIVE_1_A', '0x701ac', '') +('PLANE_SURFLIVE_2_A', '0x702ac', '') +('PLANE_SURFLIVE_3_A', '0x703ac', '') +('PLANE_WM_1_A_0', '0x70240', '') +('PLANE_WM_1_A_1', '0x70244', '') +('PLANE_WM_1_A_2', '0x70248', '') +('PLANE_WM_1_A_3', '0x7024c', '') +('PLANE_WM_1_A_4', '0x70250', '') +('PLANE_WM_1_A_5', '0x70254', '') +('PLANE_WM_1_A_6', '0x70258', '') +('PLANE_WM_1_A_7', '0x7025c', '') +('PLANE_WM_2_A_0', '0x70340', '') +('PLANE_WM_2_A_1', '0x70344', '') +('PLANE_WM_2_A_2', '0x70348', '') +('PLANE_WM_2_A_3', '0x7034c', '') +('PLANE_WM_2_A_4', '0x70350', '') +('PLANE_WM_2_A_5', '0x70354', '') +('PLANE_WM_2_A_6', '0x70358', '') +('PLANE_WM_2_A_7', '0x7035c', '') +('PLANE_WM_3_A_0', '0x70440', '') +('PLANE_WM_3_A_1', '0x70444', '') +('PLANE_WM_3_A_2', '0x70448', '') +('PLANE_WM_3_A_3', '0x7044c', '') +('PLANE_WM_3_A_4', '0x70450', '') +('PLANE_WM_3_A_5', '0x70454', '') +('PLANE_WM_3_A_6', '0x70458', '') +('PLANE_WM_3_A_7', '0x7045c', '') +('PLANE_WM_TRANS_1_A', '0x70268', '') +('PLANE_WM_TRANS_2_A', '0x70368', '') +('PLANE_WM_TRANS_3_A', '0x70468', '') +# PIPE_A_CURSOR_PLANE +('CUR_BUF_CFG_A', '0x7017c', '') +('CUR_BASE_A', '0x70084', '') +('CUR_CTL_A', '0x70080', '') +('CUR_FBC_CTL_A', '0x700a0', '') +('CUR_POS_A', '0x70088', '') +('CUR_SURFLIVE_A', '0x700ac', '') +('CUR_WM_A_0', '0x70140', '') +('CUR_WM_A_1', '0x70144', '') +('CUR_WM_A_2', '0x70148', '') +('CUR_WM_A_3', '0x7014c', '') +('CUR_WM_A_4', '0x70150', '') +('CUR_WM_A_5', '0x70154', '') +('CUR_WM_A_6', '0x70158', '') +('CUR_WM_A_7', '0x7015c', '') +('CUR_WM_TRANS_A', '0x70168', '') +# PIPE_SCALER_A +('PS_CTRL_1_A', '0x68180', '') +('PS_CTRL_2_A', '0x68280', '') +('PS_ECC_STAT_1_A', '0x681d0', '') +('PS_ECC_STAT_2_A', '0x682d0', '') +('PS_HPHASE_1_A', '0x68194', '') +('PS_HPHASE_2_A', '0x68294', '') +('PS_HSCALE_1_A', '0x68190', '') +('PS_HSCALE_2_A', '0x68290', '') +('PS_PWR_GATE_1_A', '0x68160', '') +('PS_PWR_GATE_2_A', '0x68260', '') +('PS_VPHASE_1_A', '0x68188', '') +('PS_VPHASE_2_A', '0x68288', '') +('PS_VSCALE_1_A', '0x68184', '') +('PS_VSCALE_2_A', '0x68284', '') +('PS_WIN_POS_1_A', '0x68170', '') +('PS_WIN_POS_2_A', '0x68270', '') +('PS_WIN_SZ_1_A', '0x68174', '') +('PS_WIN_SZ_2_A', '0x68274', '') +# PIPE_B_PLANE +('PLANE_BUF_CFG_1_B', '0x7127c', '') +('PLANE_BUF_CFG_2_B', '0x7137c', '') +('PLANE_BUF_CFG_3_B', '0x7147c', '') +('PLANE_NV12_BUF_CFG_1_B', '0x71278', '') +('PLANE_NV12_BUF_CFG_2_B', '0x71378', '') +('PLANE_NV12_BUF_CFG_3_B', '0x71478', '') +('PLANE_CTL_1_B', '0x71180', '') +('PLANE_CTL_2_B', '0x71280', '') +('PLANE_CTL_3_B', '0x71380', '') +('PLANE_KEYMAX_1_B', '0x711a0', '') +('PLANE_KEYMAX_2_B', '0x712a0', '') +('PLANE_KEYMAX_3_B', '0x713a0', '') +('PLANE_KEYMSK_1_B', '0x71198', '') +('PLANE_KEYMSK_2_B', '0x71298', '') +('PLANE_KEYMSK_3_B', '0x71398', '') +('PLANE_KEYVAL_1_B', '0x71194', '') +('PLANE_KEYVAL_2_B', '0x71294', '') +('PLANE_KEYVAL_3_B', '0x71394', '') +('PLANE_OFFSET_1_B', '0x711a4', '') +('PLANE_OFFSET_2_B', '0x712a4', '') +('PLANE_OFFSET_3_B', '0x713a4', '') +('PLANE_AUX_OFFSET_1_B', '0x711c4', '') +('PLANE_AUX_OFFSET_2_B', '0x712c4', '') +('PLANE_AUX_OFFSET_3_B', '0x713c4', '') +('PLANE_POS_1_B', '0x7118c', '') +('PLANE_POS_2_B', '0x7128c', '') +('PLANE_POS_3_B', '0x7138c', '') +('PLANE_SIZE_1_B', '0x71190', '') +('PLANE_SIZE_2_B', '0x71290', '') +('PLANE_SIZE_3_B', '0x71390', '') +('PLANE_STRIDE_1_B', '0x71188', '') +('PLANE_STRIDE_2_B', '0x71288', '') +('PLANE_STRIDE_3_B', '0x71388', '') +('PLANE_SURF_1_B', '0x7119c', '') +('PLANE_SURF_2_B', '0x7129c', '') +('PLANE_SURF_3_B', '0x7139c', '') +('PLANE_SURFLIVE_1_B', '0x711ac', '') +('PLANE_SURFLIVE_2_B', '0x712ac', '') +('PLANE_SURFLIVE_3_B', '0x713ac', '') +('PLANE_WM_1_B_0', '0x71240', '') +('PLANE_WM_1_B_1', '0x71244', '') +('PLANE_WM_1_B_2', '0x71248', '') +('PLANE_WM_1_B_3', '0x7124c', '') +('PLANE_WM_1_B_4', '0x71250', '') +('PLANE_WM_1_B_5', '0x71254', '') +('PLANE_WM_1_B_6', '0x71258', '') +('PLANE_WM_1_B_7', '0x7125c', '') +('PLANE_WM_2_B_0', '0x71340', '') +('PLANE_WM_2_B_1', '0x71344', '') +('PLANE_WM_2_B_2', '0x71348', '') +('PLANE_WM_2_B_3', '0x7134c', '') +('PLANE_WM_2_B_4', '0x71350', '') +('PLANE_WM_2_B_5', '0x71354', '') +('PLANE_WM_2_B_6', '0x71358', '') +('PLANE_WM_2_B_7', '0x7135c', '') +('PLANE_WM_3_B_0', '0x71440', '') +('PLANE_WM_3_B_1', '0x71444', '') +('PLANE_WM_3_B_2', '0x71448', '') +('PLANE_WM_3_B_3', '0x7144c', '') +('PLANE_WM_3_B_4', '0x71450', '') +('PLANE_WM_3_B_5', '0x71454', '') +('PLANE_WM_3_B_6', '0x71458', '') +('PLANE_WM_3_B_7', '0x7145c', '') +('PLANE_WM_TRANS_1_B', '0x71268', '') +('PLANE_WM_TRANS_2_B', '0x71368', '') +('PLANE_WM_TRANS_3_B', '0x71468', '') +# PIPE_B_CURSOR_PLANE +('CUR_BUF_CFG_B', '0x7117c', '') +('CUR_BASE_B', '0x71084', '') +('CUR_CTL_B', '0x71080', '') +('CUR_FBC_CTL_B', '0x710a0', '') +('CUR_POS_B', '0x71088', '') +('CUR_SURFLIVE_B', '0x710ac', '') +('CUR_WM_B_0', '0x71140', '') +('CUR_WM_B_1', '0x71144', '') +('CUR_WM_B_2', '0x71148', '') +('CUR_WM_B_3', '0x7114c', '') +('CUR_WM_B_4', '0x71150', '') +('CUR_WM_B_5', '0x71154', '') +('CUR_WM_B_6', '0x71158', '') +('CUR_WM_B_7', '0x7115c', '') +('CUR_WM_TRANS_B', '0x71168', '') +# PIPE_SCALER_B +('PS_CTRL_1_B', '0x68980', '') +('PS_CTRL_2_B', '0x68a80', '') +('PS_ECC_STAT_1_B', '0x689d0', '') +('PS_ECC_STAT_2_B', '0x68ad0', '') +('PS_HPHASE_1_B', '0x68994', '') +('PS_HPHASE_2_B', '0x68a94', '') +('PS_HSCALE_1_B', '0x68990', '') +('PS_HSCALE_2_B', '0x68a90', '') +('PS_PWR_GATE_1_B', '0x68960', '') +('PS_PWR_GATE_2_B', '0x68a60', '') +('PS_VPHASE_1_B', '0x68988', '') +('PS_VPHASE_2_B', '0x68a88', '') +('PS_VSCALE_1_B', '0x68984', '') +('PS_VSCALE_2_B', '0x68a84', '') +('PS_WIN_POS_1_B', '0x68970', '') +('PS_WIN_POS_2_B', '0x68a70', '') +# PIPE_C_PLANE +('PLANE_BUF_CFG_1_C', '0x7227c', '') +('PLANE_BUF_CFG_2_C', '0x7237c', '') +('PLANE_BUF_CFG_3_C', '0x7247c', '') +('PLANE_NV12_BUF_CFG_1_C', '0x72278', '') +('PLANE_NV12_BUF_CFG_2_C', '0x72378', '') +('PLANE_NV12_BUF_CFG_3_C', '0x72478', '') +('PLANE_AUX_DIST_1_C', '0x721c0', '') +('PLANE_AUX_DIST_2_C', '0x722c0', '') +('PLANE_AUX_DIST_3_C', '0x723c0', '') +('PLANE_CTL_1_C', '0x72180', '') +('PLANE_CTL_2_C', '0x72280', '') +('PLANE_CTL_3_C', '0x72380', '') +('PLANE_KEYMAX_1_C', '0x721a0', '') +('PLANE_KEYMAX_2_C', '0x722a0', '') +('PLANE_KEYMAX_3_C', '0x723a0', '') +('PLANE_KEYMSK_1_C', '0x72198', '') +('PLANE_KEYMSK_2_C', '0x72298', '') +('PLANE_KEYMSK_3_C', '0x72398', '') +('PLANE_KEYVAL_1_C', '0x72194', '') +('PLANE_KEYVAL_2_C', '0x72294', '') +('PLANE_KEYVAL_3_C', '0x72394', '') +('PLANE_OFFSET_1_C', '0x721a4', '') +('PLANE_OFFSET_2_C', '0x722a4', '') +('PLANE_OFFSET_3_C', '0x723a4', '') +('PLANE_AUX_OFFSET_1_C', '0x721c4', '') +('PLANE_AUX_OFFSET_2_C', '0x722c4', '') +('PLANE_AUX_OFFSET_3_C', '0x723c4', '') +('PLANE_POS_1_C', '0x7218c', '') +('PLANE_POS_2_C', '0x7228c', '') +('PLANE_POS_3_C', '0x7238c', '') +('PLANE_SIZE_1_C', '0x72190', '') +('PLANE_SIZE_2_C', '0x72290', '') +('PLANE_SIZE_3_C', '0x72390', '') +('PLANE_STRIDE_1_C', '0x72188', '') +('PLANE_STRIDE_2_C', '0x72288', '') +('PLANE_STRIDE_3_C', '0x72388', '') +('PLANE_SURF_1_C', '0x7219c', '') +('PLANE_SURF_2_C', '0x7229c', '') +('PLANE_SURF_3_C', '0x7239c', '') +('PLANE_SURFLIVE_1_C', '0x721ac', '') +('PLANE_SURFLIVE_2_C', '0x722ac', '') +('PLANE_SURFLIVE_3_C', '0x723ac', '') +('PLANE_WM_1_C_0', '0x72240', '') +('PLANE_WM_1_C_1', '0x72244', '') +('PLANE_WM_1_C_2', '0x72248', '') +('PLANE_WM_1_C_3', '0x7224c', '') +('PLANE_WM_1_C_4', '0x72250', '') +('PLANE_WM_1_C_5', '0x72254', '') +('PLANE_WM_1_C_6', '0x72258', '') +('PLANE_WM_1_C_7', '0x7225c', '') +('PLANE_WM_2_C_0', '0x72340', '') +('PLANE_WM_2_C_1', '0x72344', '') +('PLANE_WM_2_C_2', '0x72348', '') +('PLANE_WM_2_C_3', '0x7234c', '') +('PLANE_WM_2_C_4', '0x72350', '') +('PLANE_WM_2_C_5', '0x72354', '') +('PLANE_WM_2_C_6', '0x72358', '') +('PLANE_WM_2_C_7', '0x7235c', '') +('PLANE_WM_3_C_0', '0x72440', '') +('PLANE_WM_3_C_1', '0x72444', '') +('PLANE_WM_3_C_2', '0x72448', '') +('PLANE_WM_3_C_3', '0x7244c', '') +('PLANE_WM_3_C_4', '0x72450', '') +('PLANE_WM_3_C_5', '0x72454', '') +('PLANE_WM_3_C_6', '0x72458', '') +('PLANE_WM_3_C_7', '0x7245c', '') +('PLANE_WM_TRANS_1_C', '0x72268', '') +('PLANE_WM_TRANS_2_C', '0x72368', '') +('PLANE_WM_TRANS_3_C', '0x72468', '') +# PIPE_C_CURSOR_PLANE +('CUR_BUF_CFG_C', '0x7217c', '') +('CUR_BASE_C', '0x72084', '') +('CUR_CTL_C', '0x72080', '') +('CUR_FBC_CTL_C', '0x720a0', '') +('CUR_POS_C', '0x72088', '') +('CUR_SURFLIVE_C', '0x720ac', '') +('CUR_WM_C_0', '0x72140', '') +('CUR_WM_C_1', '0x72144', '') +('CUR_WM_C_2', '0x72148', '') +('CUR_WM_C_3', '0x7214c', '') +('CUR_WM_C_4', '0x72150', '') +('CUR_WM_C_5', '0x72154', '') +('CUR_WM_C_6', '0x72158', '') +('CUR_WM_C_7', '0x7215c', '') +('CUR_WM_TRANS_C', '0x72168', '') +# PIPE_SCALER_C +('PS_CTRL_1_C', '0x69180', '') +('PS_ECC_STAT_1_C', '0x691d0', '') +('PS_HPHASE_1_C', '0x69194', '') +('PS_HSCALE_1_C', '0x69190', '') +('PS_PWR_GATE_1_C', '0x69160', '') +('PS_VPHASE_1_C', '0x69188', '') +('PS_VSCALE_1_C', '0x69184', '') +('PS_WIN_POS_1_C', '0x69170', '') +('PS_WIN_SZ_1_C', '0x69174', '') +# TRANSCODER_EDP_CONTROL +('TRANS_CONF_EDP', '0x7f008', '') +# TRANSCODER_EDP_TIMING +('TRANS_HBLANK_EDP', '0x6f004', '') +('TRANS_HSYNC_EDP', '0x6f008', '') +('TRANS_HTOTAL_EDP', '0x6f000', '') +('TRANS_SPACE_EDP', '0x6f024', '') +('TRANS_VBLANK_EDP', '0x6f010', '') +('TRANS_VSYNC_EDP', '0x6f014', '') +('TRANS_VSYNCSHIFT_EDP', '0x6f028', '') +('TRANS_VTOTAL_EDP', '0x6f00c', '') +# TRANSCODER_EDP_M_N +('TRANS_DATAM1_EDP', '0x6f030', '') +('TRANS_DATAN1_EDP', '0x6f034', '') +('TRANS_LINKM1_EDP', '0x6f040', '') +('TRANS_LINKN1_EDP', '0x6f044', '') +# TRANSCODER_EDP_DDI_CONTROL +('TRANS_DDI_FUNC_CTL_EDP', '0x6f400', '') +('TRANS_MSA_MISC_EDP', '0x6f410', '') +# TRANSCODER_A_CONTROL +('TRANS_CONF_A', '0x70008', '') +# TRANSCODER_A_TIMING +('TRANS_HBLANK_A', '0x60004', '') +('TRANS_HSYNC_A', '0x60008', '') +('TRANS_HTOTAL_A', '0x60000', '') +('TRANS_MULT_A', '0x6002c', '') +('TRANS_SPACE_A', '0x60024', '') +('TRANS_VBLANK_A', '0x60010', '') +('TRANS_VSYNC_A', '0x60014', '') +('TRANS_VSYNCSHIFT_A', '0x60028', '') +('TRANS_VTOTAL_A', '0x6000c', '') +# TRANSCODER_A_M_N +('TRANS_DATAM1_A', '0x60030', '') +('TRANS_DATAN1_A', '0x60034', '') +('TRANS_LINKM1_A', '0x60040', '') +('TRANS_LINKN1_A', '0x60044', '') +# TRANSCODER_A_DDI_CONTROL +('TRANS_DDI_FUNC_CTL_A', '0x60400', '') +('TRANS_MSA_MISC_A', '0x60410', '') +# TRANSCODER_B_CONTROL +('TRANS_CONF_B', '0x71008', '') +# TRANSCODER_B_TIMING +('TRANS_HBLANK_B', '0x61004', '') +('TRANS_HSYNC_B', '0x61008', '') +('TRANS_HTOTAL_B', '0x61000', '') +('TRANS_MULT_B', '0x6102c', '') +('TRANS_SPACE_B', '0x61024', '') +('TRANS_VBLANK_B', '0x61010', '') +('TRANS_VSYNC_B', '0x61014', '') +('TRANS_VSYNCSHIFT_B', '0x61028', '') +('TRANS_VTOTAL_B', '0x6100c', '') +# TRANSCODER_B_M_N +('TRANS_DATAM1_B', '0x61030', '') +('TRANS_DATAN1_B', '0x61034', '') +('TRANS_LINKM1_B', '0x61040', '') +('TRANS_LINKN1_B', '0x61044', '') +# TRANSCODER_B_DDI_CONTROL +('TRANS_DDI_FUNC_CTL_B', '0x61400', '') +('TRANS_MSA_MISC_B', '0x61410', '') +# TRANSCODER_C_CONTROL +('TRANS_CONF_C', '0x72008', '') +# TRANSCODER_C_TIMING +('TRANS_HBLANK_C', '0x62004', '') +('TRANS_HSYNC_C', '0x62008', '') +('TRANS_HTOTAL_C', '0x62000', '') +('TRANS_MULT_C', '0x6202c', '') +('TRANS_SPACE_C', '0x62024', '') +('TRANS_VBLANK_C', '0x62010', '') +('TRANS_VSYNC_C', '0x62014', '') +('TRANS_VSYNCSHIFT_C', '0x62028', '') +('TRANS_VTOTAL_C', '0x6200c', '') +# TRANSCODER_C_M_N +('TRANS_DATAM1_C', '0x62030', '') +('TRANS_DATAN1_C', '0x62034', '') +('TRANS_LINKM1_C', '0x62040', '') +('TRANS_LINKN1_C', '0x62044', '') +# TRANSCODER_C_DDI_CONTROL +('TRANS_DDI_FUNC_CTL_C', '0x62400', '') +('TRANS_MSA_MISC_C', '0x62410', '') +# WATERMARK +('WM_LINETIME_A', '0x45270', '') +('WM_LINETIME_B', '0x45274', '') +('WM_LINETIME_C', '0x45278', '') +('WM_MISC', '0x45260', '') diff --git a/tools/registers/skl_powerwells.txt b/tools/registers/skl_powerwells.txt new file mode 100644 index 00000000..0f7defb4 --- /dev/null +++ b/tools/registers/skl_powerwells.txt @@ -0,0 +1,4 @@ +('PWR_WELL_BIOS', '0x00045400', '') +('PWR_WELL_DRIVER', '0x00045404', '') +('PWR_WELL_KVM', '0x00045408', '') +('PWR_WELL_DEBUG', '0x0004540c', '') diff --git a/tools/registers/skylake b/tools/registers/skylake new file mode 100644 index 00000000..c9d9cefd --- /dev/null +++ b/tools/registers/skylake @@ -0,0 +1,4 @@ +gen8_interrupt.txt +gen8_other.txt +skl_powerwells.txt +skl_display.txt diff --git a/tools/registers/valleyview b/tools/registers/valleyview new file mode 100644 index 00000000..2611a982 --- /dev/null +++ b/tools/registers/valleyview @@ -0,0 +1,7 @@ +vlv_pipe_a.txt +vlv_pipe_b.txt +vlv_display_base.txt +vlv_dpio_phy.txt +vlv_dsi.txt +vlv_flisdsi.txt +gen7_other.txt diff --git a/tools/registers/vlv_display_base.txt b/tools/registers/vlv_display_base.txt new file mode 100644 index 00000000..5bd855a7 --- /dev/null +++ b/tools/registers/vlv_display_base.txt @@ -0,0 +1,180 @@ +('DPFLIPSTAT', '0x70028', '0x180000') +('DPINVGTT', '0x7002C', '0x180000') + +('DSPARB', '0x70030', '0x180000') +('DSPARB2', '0x70060', '0x180000') + +('DSPHOWM', '0x70064', '0x180000') +('DSPHOWM1', '0x70068', '0x180000') +('FW1', '0x70034', '0x180000') +('FW2', '0x70038', '0x180000') +('FW3', '0x7003C', '0x180000') +('FW4', '0x70070', '0x180000') +('FW5', '0x70074', '0x180000') +('FW6', '0x70078', '0x180000') +('FW7', '0x7007C', '0x180000') + +('DDL1', '0x70050', '0x180000') +('DDL2', '0x70054', '0x180000') + +('VGACNTRL', '0x71400', '0x180000') + +('CBR1', '0x70400', '0x180000') +('CBR2', '0x70404', '0x180000') +('CBR3', '0x7040C', '0x180000') +('CBR4', '0x70450', '0x180000') +('CCBR', '0x70408', '0x180000') + +('SWF00', '0x70410', '0x180000') +('SWF01', '0x70414', '0x180000') +('SWF02', '0x70418', '0x180000') +('SWF03', '0x7041C', '0x180000') +('SWF04', '0x70420', '0x180000') +('SWF05', '0x70424', '0x180000') +('SWF06', '0x70428', '0x180000') +('SWF07', '0x7042C', '0x180000') +('SWF08', '0x70430', '0x180000') +('SWF09', '0x70434', '0x180000') +('SWF0A', '0x70438', '0x180000') +('SWF0B', '0x7043C', '0x180000') +('SWF0C', '0x70440', '0x180000') +('SWF0D', '0x70444', '0x180000') +('SWF0E', '0x70448', '0x180000') +('SWF0F', '0x7044C', '0x180000') +('SWF10', '0x71410', '0x180000') +('SWF11', '0x71414', '0x180000') +('SWF12', '0x71418', '0x180000') +('SWF13', '0x7141C', '0x180000') +('SWF14', '0x71420', '0x180000') +('SWF15', '0x71424', '0x180000') +('SWF16', '0x71428', '0x180000') +('SWF17', '0x7142C', '0x180000') +('SWF18', '0x71430', '0x180000') +('SWF19', '0x71434', '0x180000') +('SWF1A', '0x71438', '0x180000') +('SWF1B', '0x7143C', '0x180000') +('SWF1C', '0x71440', '0x180000') +('SWF1D', '0x71444', '0x180000') +('SWF1E', '0x71448', '0x180000') +('SWF1F', '0x7144C', '0x180000') +('SWF30', '0x72414', '0x180000') +('SWF31', '0x72418', '0x180000') +('SWF32', '0x7241C', '0x180000') + +('PCSRC', '0x73000', '0x180000') +('PCSTAT', '0x73004', '0x180000') +('PCSRC2', '0x73008', '0x180000') +('PCSTAT2', '0x7300C', '0x180000') + +('PFIT_CONTROL', '0x61230', '0x180000') +('PFIT_PGM_RATIOS', '0x61234', '0x180000') +('PFIT_AUTO_RATION', '0x61238', '0x180000') +('PFIT_INIT_PHASE', '0x6123C', '0x180000') + +('GPIOCTL_0', '0x5010', '0x180000') +('GPIOCTL_1', '0x5014', '0x180000') +('GPIOCTL_2', '0x5018', '0x180000') +('GPIOCTL_3', '0x501C', '0x180000') +('GPIOCTL_4', '0x5020', '0x180000') + +('GMBUS0', '0x5100', '0x180000') +('GMBUS1', '0x5104', '0x180000') +('GMBUS2', '0x5108', '0x180000') +('GMBUS3', '0x510C', '0x180000') +('GMBUS4', '0x5110', '0x180000') +('GMBUS5', '0x5120', '0x180000') +('GMBUS6', '0x5130', '0x180000') +('GMBUS7', '0x5134', '0x180000') + +('RAWCLK_FREQ', '0x6024', '0x180000') +('GMBUSFREQ', '0x6510', '0x180000') +('DSPCLK_GATE_D', '0x6200', '0x180000') +('RAMCLK_GATE_D', '0x6210', '0x180000') +('D_STATE', '0x6104', '0x180000') +('DPPSR_CGDIS', '0x6204', '0x180000') +('FW_BLC_SELF', '0x6500', '0x180000') +('MI_ARB', '0x6504', '0x180000') +('CZCLK_CDCLK_FREQ_RATIO', '0x6508', '0x180000') +('GCI_CONTROL', '0x650C', '0x180000') + +('ADPA', '0x61100', '0x180000') +('CRTIO_DFX', '0x61104', '0x180000') + +('PORT_HOTPLUG_EN', '0x61110', '0x180000') +('PORT_HOTPLUG_STAT', '0x61114', '0x180000') + +('HDMIB', '0x61140', '0x180000') +('HDMIC', '0x61160', '0x180000') + +('DP2', '0x61154', '0x180000') +('DIGITAL_HPD_CTRL', '0x61164', '0x180000') +('DV_DETERM', '0x61168', '0x180000') + +('DP_AUX_CH_AKSV_HI', '0x64130', '0x180000') +('DP_AUX_CH_AKSV_LO', '0x64134', '0x180000') + +('DP_B', '0x64100', '0x180000') +('DPB_AUX_CH_CTL', '0x64110', '0x180000') +('DPB_AUX_CH_DATA1', '0x64114', '0x180000') +('DPB_AUX_CH_DATA2', '0x64118', '0x180000') +('DPB_AUX_CH_DATA3', '0x6411C', '0x180000') +('DPB_AUX_CH_DATA4', '0x64120', '0x180000') +('DPB_AUX_CH_DATA5', '0x64124', '0x180000') +('DPB_AUX_TST', '0x64150', '0x180000') + +('DP_C', '0x64200', '0x180000') +('DPC_AUX_CH_CTL', '0x64210', '0x180000') +('DPC_AUX_CH_DATA1', '0x64214', '0x180000') +('DPC_AUX_CH_DATA2', '0x64218', '0x180000') +('DPC_AUX_CH_DATA3', '0x6421C', '0x180000') +('DPC_AUX_CH_DATA4', '0x64220', '0x180000') +('DPC_AUX_CH_DATA5', '0x64224', '0x180000') +('DPC_AUX_TST', '0x64228', '0x180000') + +('DPIO_BONUS0', '0x64138', '0x180000') +('DPIO_BONUS1', '0x6413C', '0x180000') +('DPIO_BONUS2', '0x64140', '0x180000') +('DPIO_BONUS0_READ_BACK', '0x64144', '0x180000') +('DPIO_BONUS1_READ_BACK', '0x64148', '0x180000') +('DPIO_BONUS2_READ_BACK', '0x6414C', '0x180000') + +('DPA_PIX_GEN_CTRL', '0x61198', '0x180000') +('DPA_PROG_PIXEL_DATA_1', '0x6119C', '0x180000') +('DPA_PROG_PIXEL_DATA_2', '0x611A0', '0x180000') +('DPA_PROG_PIXEL_DATA_3', '0x611A4', '0x180000') +('DPA_PROG_PIXEL_DATA_4', '0x611A8', '0x180000') + +('DPB_PIX_GEN_CTRL', '0x611B0', '0x180000') +('DPB_PROG_PIXEL_DATA_1', '0x611B4', '0x180000') +('DPB_PROG_PIXEL_DATA_2', '0x611B8', '0x180000') +('DPB_PROG_PIXEL_DATA_3', '0x611BC', '0x180000') +('DPB_PROG_PIXEL_DATA_4', '0x611C0', '0x180000') + +('AUD_VID_DID', '0x62020', '0x180000') +('AUD_RID', '0x62024', '0x180000') +('AUD_PWRST', '0x6204C', '0x180000') +('AUD_PORT_EN_HD_CFG', '0x6207C', '0x180000') +('AUD_OUT_CH_STR', '0x62088', '0x180000') +('AUD_PINW_CONNLNG_LIST', '0x620A8', '0x180000') +('AUD_PINW_CONNLNG_SEL', '0x620AC', '0x180000') +('AUD_CNTL_ST2', '0x620C0', '0x180000') +('AUD_HDMIW_STATUS', '0x620D4', '0x180000') +('AUD_SSID_DBG', '0x62F00', '0x180000') +('AUD_PWST1_DBG', '0x62F04', '0x180000') +('AUD_PWST2_DBG', '0x62F14', '0x180000') +('AUD_PORT_EN_B_DBG', '0x62F20', '0x180000') +('AUD_PWST3_DBG', '0x62F24', '0x180000') +('AUD_PORT_EN_C_DBG', '0x62F28', '0x180000') +('AUD_PORT_EN_D_DBG', '0x62F2C', '0x180000') +('AUD_CHICKENBIT', '0x62F38', '0x180000') +('AUD_CNTL_ST_B_DBG', '0x62F60', '0x180000') +('AUD_HDMIW_INFOFR_B_DBG', '0x62F64', '0x180000') +('AUD_CNTL_ST_C_DBG', '0x62F70', '0x180000') +('AUD_HDMIW_INFOFR_C_DBG', '0x62F74', '0x180000') +('AUD_CNTL_ST_D_DBG', '0x62F80', '0x180000') +('AUD_HDMIW_INFOFR_D_DBG', '0x62F84', '0x180000') +('AUD_CONFIG_DEFAULT2_REG_PORTB', '0x62F88', '0x180000') +('AUD_CONFIG_DEFAULT2_REG_PORTC', '0x62F8C', '0x180000') +('AUD_CONFIG_DEFAULT2_REG_PORTD', '0x62F90', '0x180000') +('AUD_MCTSA', '0x62F94', '0x180000') +('AUD_MCTSB', '0x62F98', '0x180000') diff --git a/tools/registers/vlv_dpio_phy.txt b/tools/registers/vlv_dpio_phy.txt new file mode 100644 index 00000000..622a6156 --- /dev/null +++ b/tools/registers/vlv_dpio_phy.txt @@ -0,0 +1,198 @@ +('PLL1_DW0', '0x8000', 'DPIO') +('PLL1_DW1', '0x8004', 'DPIO') +('PLL1_DW2', '0x8008', 'DPIO') +('PLL1_DW3', '0x800C', 'DPIO') +('PLL1_DW4', '0x8010', 'DPIO') +('PLL1_DW5', '0x8014', 'DPIO') +('PLL1_DW6', '0x8018', 'DPIO') +('PLL1_DW7', '0x801C', 'DPIO') +('PLL2_DW0', '0x8020', 'DPIO') +('PLL2_DW1', '0x8024', 'DPIO') +('PLL2_DW2', '0x8028', 'DPIO') +('PLL2_DW3', '0x802C', 'DPIO') +('PLL2_DW4', '0x8030', 'DPIO') +('PLL2_DW5', '0x8034', 'DPIO') +('PLL2_DW6', '0x8038', 'DPIO') +('PLL2_DW7', '0x803C', 'DPIO') +('PLL1_EXT_DW0', '0x8040', 'DPIO') +('PLL1_EXT_DW1', '0x8044', 'DPIO') +('PLL1_EXT_DW2', '0x8048', 'DPIO') +('PLL1_EXT_DW3', '0x804C', 'DPIO') +('PLL1_EXT_DW4', '0x8050', 'DPIO') +('PLL1_EXT_DW5', '0x8054', 'DPIO') +('PLL1_EXT_DW6', '0x8058', 'DPIO') +('PLL1_EXT_DW7', '0x805C', 'DPIO') +('PLL2_EXT_DW0', '0x8060', 'DPIO') +('PLL2_EXT_DW1', '0x8064', 'DPIO') +('PLL2_EXT_DW2', '0x8068', 'DPIO') +('PLL2_EXT_DW3', '0x806C', 'DPIO') +('PLL2_EXT_DW4', '0x8070', 'DPIO') +('PLL2_EXT_DW5', '0x8074', 'DPIO') +('PLL2_EXT_DW6', '0x8078', 'DPIO') +('PLL2_EXT_DW7', '0x807C', 'DPIO') +('REF_DW0', '0x80A0', 'DPIO') +('REF_DW1', '0x80A4', 'DPIO') +('REF_DW2', '0x80A8', 'DPIO') +('REF_DW3', '0x80AC', 'DPIO') +('REF_DW4', '0x80B0', 'DPIO') +('REF_DW5', '0x80B4', 'DPIO') +('REF_DW6', '0x80B8', 'DPIO') +('REF_DW7', '0x80BC', 'DPIO') +('REF_DW8', '0x80C0', 'DPIO') +('REF_DW9', '0x80C4', 'DPIO') +('REF_DW10', '0x80C8', 'DPIO') +('REF_DW11', '0x80CC', 'DPIO') +('REF_DW12', '0x80D0', 'DPIO') +('REF_DW13', '0x80D4', 'DPIO') +('REF_DW14', '0x80D8', 'DPIO') +('REF_DW15', '0x80DC', 'DPIO') +('CL_DW0', '0x8100', 'DPIO') +('CL_DW1', '0x8104', 'DPIO') +('CL_DW2', '0x8108', 'DPIO') +('CL_DW3', '0x810C', 'DPIO') +('CL_DW4', '0x8110', 'DPIO') +('CL_DW5', '0x8114', 'DPIO') +('CL_DW6', '0x8118', 'DPIO') +('CL_DW7', '0x811C', 'DPIO') +('CL_DW8', '0x8120', 'DPIO') +('CL_DW9', '0x8124', 'DPIO') +('CL_DW10', '0x8128', 'DPIO') +('CL_DW11', '0x812C', 'DPIO') +('CL_DW12', '0x8130', 'DPIO') +('CL_DW13', '0x8134', 'DPIO') +('CL_DW14', '0x8138', 'DPIO') +('CL_DW15', '0x813C', 'DPIO') +('CL_DW16', '0x8140', 'DPIO') +('CL_DW17', '0x8144', 'DPIO') +('CL_DW18', '0x8148', 'DPIO') +('CL_DW19', '0x814C', 'DPIO') +('CL_DW20', '0x8150', 'DPIO') +('CL_DW21', '0x8154', 'DPIO') +('CL_DW22', '0x8158', 'DPIO') +('CL_DW23', '0x815C', 'DPIO') +('CL_DW24', '0x8160', 'DPIO') +('CL_DW25', '0x8164', 'DPIO') +('CL_DW26', '0x8168', 'DPIO') +('CL_DW27', '0x816C', 'DPIO') +('CL_DW28', '0x8170', 'DPIO') +('CL_DW29', '0x8174', 'DPIO') +('CL_DW30', '0x8178', 'DPIO') +('CL_DW31', '0x817C', 'DPIO') +('PCS01_CH0_DW0', '0x0200', 'DPIO') +('PCS01_CH0_DW1', '0x0204', 'DPIO') +('PCS01_CH0_DW2', '0x0208', 'DPIO') +('PCS01_CH0_DW3', '0x020C', 'DPIO') +('PCS01_CH0_DW4', '0x0210', 'DPIO') +('PCS01_CH0_DW5', '0x0214', 'DPIO') +('PCS01_CH0_DW6', '0x0218', 'DPIO') +('PCS01_CH0_DW7', '0x021C', 'DPIO') +('PCS01_CH0_DW8', '0x0220', 'DPIO') +('PCS01_CH0_DW9', '0x0224', 'DPIO') +('PCS01_CH0_DW10', '0x0228', 'DPIO') +('PCS01_CH0_DW11', '0x022C', 'DPIO') +('PCS01_CH0_DW12', '0x0230', 'DPIO') +('PCS01_CH0_DW13', '0x0234', 'DPIO') +('PCS01_CH0_DW14', '0x0238', 'DPIO') +('PCS01_CH0_DW15', '0x023C', 'DPIO') +('PCS01_CH0_DW16', '0x0240', 'DPIO') +('PCS01_CH0_DW17', '0x0244', 'DPIO') +('PCS01_CH0_DW18', '0x0248', 'DPIO') +('PCS01_CH0_DW19', '0x024C', 'DPIO') +('PCS01_CH0_DW20', '0x0250', 'DPIO') +('PCS01_CH0_DW21', '0x0254', 'DPIO') +('PCS01_CH0_DW22', '0x0258', 'DPIO') +('PCS01_CH0_DW23', '0x025C', 'DPIO') +('PCS01_CH0_DW24', '0x0260', 'DPIO') +('TX0_CH0_DW0', '0x0080', 'DPIO') +('TX0_CH0_DW1', '0x0084', 'DPIO') +('TX0_CH0_DW2', '0x0088', 'DPIO') +('TX0_CH0_DW3', '0x008C', 'DPIO') +('TX0_CH0_DW4', '0x0090', 'DPIO') +('TX0_CH0_DW5', '0x0094', 'DPIO') +('TX0_CH0_DW6', '0x0098', 'DPIO') +('TX0_CH0_DW7', '0x009C', 'DPIO') +('TX0_CH0_DW8', '0x00A0', 'DPIO') +('TX0_CH0_DW9', '0x00A4', 'DPIO') +('TX0_CH0_DW10', '0x00A8', 'DPIO') +('TX0_CH0_DW11', '0x00AC', 'DPIO') +('TX0_CH0_DW12', '0x00B0', 'DPIO') +('TX0_CH0_DW13', '0x00B4', 'DPIO') +('TX0_CH0_DW14', '0x00B8', 'DPIO') +('TX0_CH0_DW15', '0x00BC', 'DPIO') +('TX0_CH0_DW16', '0x00C0', 'DPIO') +('TX1_CH0_DW0', '0x0280', 'DPIO') +('TX1_CH0_DW1', '0x0284', 'DPIO') +('TX1_CH0_DW2', '0x0288', 'DPIO') +('TX1_CH0_DW3', '0x028C', 'DPIO') +('TX1_CH0_DW4', '0x0290', 'DPIO') +('TX1_CH0_DW5', '0x0294', 'DPIO') +('TX1_CH0_DW6', '0x0298', 'DPIO') +('TX1_CH0_DW7', '0x029C', 'DPIO') +('TX1_CH0_DW8', '0x02A0', 'DPIO') +('TX1_CH0_DW9', '0x02A4', 'DPIO') +('TX1_CH0_DW10', '0x02A8', 'DPIO') +('TX1_CH0_DW11', '0x02AC', 'DPIO') +('TX1_CH0_DW12', '0x02B0', 'DPIO') +('TX1_CH0_DW13', '0x02B4', 'DPIO') +('TX1_CH0_DW14', '0x02B8', 'DPIO') +('TX1_CH0_DW15', '0x02BC', 'DPIO') +('TX1_CH0_DW16', '0x02C0', 'DPIO') +('PCS23_CH0_DW0', '0x0400', 'DPIO') +('PCS23_CH0_DW1', '0x0404', 'DPIO') +('PCS23_CH0_DW2', '0x0408', 'DPIO') +('PCS23_CH0_DW3', '0x040C', 'DPIO') +('PCS23_CH0_DW4', '0x0410', 'DPIO') +('PCS23_CH0_DW5', '0x0414', 'DPIO') +('PCS23_CH0_DW6', '0x0418', 'DPIO') +('PCS23_CH0_DW7', '0x041C', 'DPIO') +('PCS23_CH0_DW8', '0x0420', 'DPIO') +('PCS23_CH0_DW9', '0x0424', 'DPIO') +('PCS23_CH0_DW10', '0x0428', 'DPIO') +('PCS23_CH0_DW11', '0x042C', 'DPIO') +('PCS23_CH0_DW12', '0x0430', 'DPIO') +('PCS23_CH0_DW13', '0x0434', 'DPIO') +('PCS23_CH0_DW14', '0x0438', 'DPIO') +('PCS23_CH0_DW15', '0x043C', 'DPIO') +('PCS23_CH0_DW16', '0x0440', 'DPIO') +('PCS23_CH0_DW17', '0x0444', 'DPIO') +('PCS23_CH0_DW18', '0x0448', 'DPIO') +('PCS23_CH0_DW19', '0x044C', 'DPIO') +('PCS23_CH0_DW20', '0x0450', 'DPIO') +('PCS23_CH0_DW21', '0x0454', 'DPIO') +('PCS23_CH0_DW22', '0x0458', 'DPIO') +('PCS23_CH0_DW23', '0x045C', 'DPIO') +('PCS23_CH0_DW24', '0x0460', 'DPIO') +('TX2_CH0_DW0', '0x0480', 'DPIO') +('TX2_CH0_DW1', '0x0484', 'DPIO') +('TX2_CH0_DW2', '0x0488', 'DPIO') +('TX2_CH0_DW3', '0x048C', 'DPIO') +('TX2_CH0_DW4', '0x0490', 'DPIO') +('TX2_CH0_DW5', '0x0494', 'DPIO') +('TX2_CH0_DW6', '0x0498', 'DPIO') +('TX2_CH0_DW7', '0x049C', 'DPIO') +('TX2_CH0_DW8', '0x04A0', 'DPIO') +('TX2_CH0_DW9', '0x04A4', 'DPIO') +('TX2_CH0_DW10', '0x04A8', 'DPIO') +('TX2_CH0_DW11', '0x04AC', 'DPIO') +('TX2_CH0_DW12', '0x04B0', 'DPIO') +('TX2_CH0_DW13', '0x04B4', 'DPIO') +('TX2_CH0_DW14', '0x04B8', 'DPIO') +('TX2_CH0_DW15', '0x04BC', 'DPIO') +('TX2_CH0_DW16', '0x04C0', 'DPIO') +('TX3_CH0_DW0', '0x0680', 'DPIO') +('TX3_CH0_DW1', '0x0684', 'DPIO') +('TX3_CH0_DW2', '0x0688', 'DPIO') +('TX3_CH0_DW3', '0x068C', 'DPIO') +('TX3_CH0_DW4', '0x0690', 'DPIO') +('TX3_CH0_DW5', '0x0694', 'DPIO') +('TX3_CH0_DW6', '0x0698', 'DPIO') +('TX3_CH0_DW7', '0x069C', 'DPIO') +('TX3_CH0_DW8', '0x06A0', 'DPIO') +('TX3_CH0_DW9', '0x06A4', 'DPIO') +('TX3_CH0_DW10', '0x06A8', 'DPIO') +('TX3_CH0_DW11', '0x06AC', 'DPIO') +('TX3_CH0_DW12', '0x06B0', 'DPIO') +('TX3_CH0_DW13', '0x06B4', 'DPIO') +('TX3_CH0_DW14', '0x06B8', 'DPIO') +('TX3_CH0_DW15', '0x06BC', 'DPIO') +('TX3_CH0_DW16', '0x06C0', 'DPIO') diff --git a/tools/registers/vlv_dsi.txt b/tools/registers/vlv_dsi.txt new file mode 100644 index 00000000..5f62e507 --- /dev/null +++ b/tools/registers/vlv_dsi.txt @@ -0,0 +1,108 @@ +('MIPIA_PORT_CTRL', '0x61190', '0x180000') +('MIPIA_TEARING_CTRL', '0x61194', '0x180000') +('MIPIA_AUTOPWG', '0x611A0', '0x180000') +('MIPIA_DEVICE_READY', '0xB000', '0x180000') +('MIPIA_INTR_STAT', '0xB004', '0x180000') +('MIPIA_INTR_EN', '0xB008', '0x180000') +('MIPIA_DSI_FUNC_PRG', '0xB00C', '0x180000') +('MIPIA_HS_TX_TIMEOUT', '0xB010', '0x180000') +('MIPIA_LP_RX_TIMEOUT', '0xB014', '0x180000') +('MIPIA_TURN_AROUND_TIMEOUT', '0xB018', '0x180000') +('MIPIA_DEVICE_RESET_TIMER', '0xB01C', '0x180000') +('MIPIA_DPI_RESOLUTION', '0xB020', '0x180000') +('MIPIA_DBI_FIFO_THROTTLE', '0xB024', '0x180000') +('MIPIA_HSYNC_PADDING_COUNT', '0xB028', '0x180000') +('MIPIA_HBP_COUNT', '0xB02C', '0x180000') +('MIPIA_HFP_COUNT', '0xB030', '0x180000') +('MIPIA_HACTIVE_AREA_COUNT', '0xB034', '0x180000') +('MIPIA_VSYNC_PADDING_COUNT', '0xB038', '0x180000') +('MIPIA_VBP_COUNT', '0xB03C', '0x180000') +('MIPIA_VFP_COUNT', '0xB040', '0x180000') +('MIPIA_HIGH_LOW_SWITCH_COUNT', '0xB044', '0x180000') +('MIPIA_DPI_CONTROL', '0xB048', '0x180000') +('MIPIA_DPI_DATA', '0xB04C', '0x180000') +('MIPIA_INIT_COUNT', '0xB050', '0x180000') +('MIPIA_MAX_RETURN_PKT_SIZE', '0xB054', '0x180000') +('MIPIA_VIDEO_MODE_FORMAT', '0xB058', '0x180000') +('MIPIA_EOT_DISABLE', '0xB05C', '0x180000') +('MIPIA_LP_BYTECLK', '0xB060', '0x180000') +('MIPIA_LP_GEN_DATA', '0xB064', '0x180000') +('MIPIA_HS_GEN_DATA', '0xB068', '0x180000') +('MIPIA_LP_GEN_CTRL', '0xB06C', '0x180000') +('MIPIA_HS_GEN_CTRL', '0xB070', '0x180000') +('MIPIA_GEN_FIFO_STAT', '0xB074', '0x180000') +('MIPIA_HS_LS_DBI_ENABLE', '0xB078', '0x180000') +('MIPIA_DPHY_PARAM', '0xB080', '0x180000') +('MIPIA_DBI_BW_CTRL', '0xB084', '0x180000') +('MIPIA_CLK_LANE_SWITCH_TIME_CNT', '0xB088', '0x180000') +('MIPIA_STOP_STATE_STALL', '0xB08C', '0x180000') +('MIPIA_INTR_STAT_REG_1', '0xB090', '0x180000') +('MIPIA_INTR_EN_REG_1', '0xB094', '0x180000') +('MIPIA_DBI_TYPEC_CTRL', '0xB100', '0x180000') +('MIPIA_CTRL', '0xB104', '0x180000') +('MIPIA_DATA_ADDRESS', '0xB108', '0x180000') +('MIPIA_DATA_LENGTH', '0xB10C', '0x180000') +('MIPIA_COMMAND_ADDRESS', '0xB110', '0x180000') +('MIPIA_COMMAND_LENGTH', '0xB114', '0x180000') +('MIPIA_READ_DATA_RETURN0', '0xB118', '0x180000') +('MIPIA_READ_DATA_RETURN1', '0xB11C', '0x180000') +('MIPIA_READ_DATA_RETURN2', '0xB120', '0x180000') +('MIPIA_READ_DATA_RETURN3', '0xB124', '0x180000') +('MIPIA_READ_DATA_RETURN4', '0xB128', '0x180000') +('MIPIA_READ_DATA_RETURN5', '0xB12C', '0x180000') +('MIPIA_READ_DATA_RETURN6', '0xB130', '0x180000') +('MIPIA_READ_DATA_RETURN7', '0xB134', '0x180000') +('MIPIA_READ_DATA_VALID', '0xB138', '0x180000') +('MIPIC_PORT_CTRL', '0x61700', '0x180000') +('MIPIC_TEARING_CTRL', '0x61704', '0x180000') +('MIPIC_DEVICE_READY', '0xB800', '0x180000') +('MIPIC_INTR_STAT', '0xB804', '0x180000') +('MIPIC_INTR_EN', '0xB808', '0x180000') +('MIPIC_DSI_FUNC_PRG', '0xB80C', '0x180000') +('MIPIC_HS_TX_TIMEOUT', '0xB810', '0x180000') +('MIPIC_LP_RX_TIMEOUT', '0xB814', '0x180000') +('MIPIC_TURN_AROUND_TIMEOUT', '0xB818', '0x180000') +('MIPIC_DEVICE_RESET_TIMER', '0xB81C', '0x180000') +('MIPIC_DPI_RESOLUTION', '0xB820', '0x180000') +('MIPIC_DBI_FIFO_THROTTLE', '0xB824', '0x180000') +('MIPIC_HSYNC_PADDING_COUNT', '0xB828', '0x180000') +('MIPIC_HBP_COUNT', '0xB82C', '0x180000') +('MIPIC_HFP_COUNT', '0xB830', '0x180000') +('MIPIC_HACTIVE_AREA_COUNT', '0xB834', '0x180000') +('MIPIC_VSYNC_PADDING_COUNT', '0xB838', '0x180000') +('MIPIC_VBP_COUNT', '0xB83C', '0x180000') +('MIPIC_VFP_COUNT', '0xB840', '0x180000') +('MIPIC_HIGH_LOW_SWITCH_COUNT', '0xB844', '0x180000') +('MIPIC_DPI_CONTROL', '0xB848', '0x180000') +('MIPIC_DPI_DATA', '0xB84C', '0x180000') +('MIPIC_INIT_COUNT', '0xB850', '0x180000') +('MIPIC_MAX_RETURN_PKT_SIZE', '0xB854', '0x180000') +('MIPIC_VIDEO_MODE_FORMAT', '0xB858', '0x180000') +('MIPIC_EOT_DISABLE', '0xB85C', '0x180000') +('MIPIC_LP_BYTECLK', '0xB860', '0x180000') +('MIPIC_LP_GEN_DATA', '0xB864', '0x180000') +('MIPIC_HS_GEN_DATA', '0xB868', '0x180000') +('MIPIC_LP_GEN_CTRL', '0xB86C', '0x180000') +('MIPIC_HS_GEN_CTRL', '0xB870', '0x180000') +('MIPIC_GEN_FIFO_STAT', '0xB874', '0x180000') +('MIPIC_HS_LS_DBI_ENABLE', '0xB878', '0x180000') +('MIPIC_DPHY_PARAM', '0xB880', '0x180000') +('MIPIC_DBI_BW_CTRL', '0xB884', '0x180000') +('MIPIC_CLK_LANE_SWITCH_TIME_CNT', '0xB888', '0x180000') +('MIPIC_STOP_STATE_STALL', '0xB88C', '0x180000') +('MIPIC_INTR_STAT_REG_1', '0xB890', '0x180000') +('MIPIC_INTR_EN_REG_1', '0xB894', '0x180000') +('MIPIC_CTRL', '0xB904', '0x180000') +('MIPIC_DATA_ADDRESS', '0xB908', '0x180000') +('MIPIC_DATA_LENGTH', '0xB90C', '0x180000') +('MIPIC_COMMAND_ADDRESS', '0xB910', '0x180000') +('MIPIC_COMMAND_LENGTH', '0xB914', '0x180000') +('MIPIC_READ_DATA_RETURN0', '0xB918', '0x180000') +('MIPIC_READ_DATA_RETURN1', '0xB91C', '0x180000') +('MIPIC_READ_DATA_RETURN2', '0xB920', '0x180000') +('MIPIC_READ_DATA_RETURN3', '0xB924', '0x180000') +('MIPIC_READ_DATA_RETURN4', '0xB928', '0x180000') +('MIPIC_READ_DATA_RETURN5', '0xB92C', '0x180000') +('MIPIC_READ_DATA_RETURN6', '0xB930', '0x180000') +('MIPIC_READ_DATA_RETURN7', '0xB934', '0x180000') +('MIPIC_READ_DATA_VALID', '0xB938', '0x180000') diff --git a/tools/registers/vlv_flisdsi.txt b/tools/registers/vlv_flisdsi.txt new file mode 100644 index 00000000..18f2b004 --- /dev/null +++ b/tools/registers/vlv_flisdsi.txt @@ -0,0 +1,39 @@ +('MIPI4DPHY_RCOMP_IOSFSB_REG0', '0x0000', 'FLISDSI') +('MIPI4DPHY_RCOMP_IOSFSB_REG1', '0x0001', 'FLISDSI') +('MIPI4DPHY_RCOMP_IOSFSB_REG2', '0x0002', 'FLISDSI') +('MIPI4DPHY_RCOMP_IOSFSB_REG3', '0x0003', 'FLISDSI') +('MIPI4DPHY_RCOMP_IOSFSB_REG4', '0x0004', 'FLISDSI') +('MIPI4DPHY_RCOMP_IOSFSB_REG5', '0x0005', 'FLISDSI') +('MIPI4DPHY_RCOMP_IOSFSB_REG6', '0x0006', 'FLISDSI') +('MIPI4DPHY_RCOMP_IOSFSB_REG7', '0x0007', 'FLISDSI') +('DSI_CFG', '0x0008', 'FLISDSI') +('DSI_DLLCOUNTCD_STATUS', '0x0009', 'FLISDSI') +('DSI_RXCDCNTRL', '0x000a', 'FLISDSI') +('DSI_HSRCOMP_STAT', '0x000b', 'FLISDSI') +('DSI_LPRCOMP_STAT', '0x000c', 'FLISDSI') +('DSI_LPRCOMP2', '0x000d', 'FLISDSI') +('DSI_LPRCOMP1', '0x000e', 'FLISDSI') +('DSI_BGCTL', '0x000f', 'FLISDSI') +('DSI_RCCCFG', '0x0010', 'FLISDSI') +('DSI_MISRDOUTLP', '0x0011', 'FLISDSI') +('DSI_RCCRCOMP', '0x0012', 'FLISDSI') +('DSI_BSCOMPARE', '0x0013', 'FLISDSI') +('DSI_RCOMPCTL1', '0x0014', 'FLISDSI') +('DSI_TXCNTRL', '0x0015', 'FLISDSI') +('DSI_MISRDOUT1', '0x0016', 'FLISDSI') +('DSI_DLLCTL2', '0x0017', 'FLISDSI') +('DSI_DLLCTL1', '0x0018', 'FLISDSI') +('DSI_ACIOCFG2', '0x0019', 'FLISDSI') +('DSI_ACIOCFG1', '0x001a', 'FLISDSI') +('DSI_ACIOSS', '0x001b', 'FLISDSI') +('DSI_ACIOERR1', '0x001c', 'FLISDSI') +('DSI_ACIOERR2', '0x001d', 'FLISDSI') +('DSI_MISRDOUT2', '0x001e', 'FLISDSI') +('DSI_RCOMPCTL2', '0x001f', 'FLISDSI') +('DSI_ALL01', '0x0020', 'FLISDSI') +('DSI_DLLCTL3', '0x0021', 'FLISDSI') +('DSI_DATAEYE1', '0x0022', 'FLISDSI') +('DSI_DATAEYE2', '0x0023', 'FLISDSI') +('DSI_DATAEYE3', '0x0024', 'FLISDSI') +('DSI_DATAEYE4', '0x0025', 'FLISDSI') +('DSI_DATAEYE5', '0x0026', 'FLISDSI') diff --git a/tools/registers/vlv_pipe_a.txt b/tools/registers/vlv_pipe_a.txt new file mode 100644 index 00000000..2b336f35 --- /dev/null +++ b/tools/registers/vlv_pipe_a.txt @@ -0,0 +1,175 @@ +('PIPEA_DSL', '0x70000', '0x180000') +('PIPEA_SLC', '0x70004', '0x180000') +('PIPEACONF', '0x70008', '0x180000') +('PIPEAGCMAXRED', '0x70010', '0x180000') +('PIPEAGCMAXGREEN', '0x70014', '0x180000') +('PIPEAGCMAXBLUE', '0x70018', '0x180000') +('PIPEASTAT', '0x70024', '0x180000') +('PIPEAFRAMECOUNT', '0x70040', '0x180000') +('PIPEAFLIPCOUNT', '0x70044', '0x180000') +('PIPEAMSAMISC', '0x70048', '0x180000') + +('DSPAADDR', '0x7017C', '0x180000') +('DSPACNTR', '0x70180', '0x180000') +('DSPALINOFF', '0x70184', '0x180000') +('DSPASTRIDE', '0x70188', '0x180000') +('DSPAKEYVAL', '0x70194', '0x180000') +('DSPAKEYMSK', '0x70198', '0x180000') +('DSPASURF', '0x7019C', '0x180000') +('DSPATILEOFF', '0x701A4', '0x180000') +('DSPASURFLIVE', '0x701AC', '0x180000') +('DSPAFLPQSTAT', '0x70200', '0x180000') + +('CURACNTR', '0x70080', '0x180000') +('CURABASE', '0x70084', '0x180000') +('CURAPOS', '0x70088', '0x180000') +('CURARESV', '0x7008C', '0x180000') +('CURAPALET0', '0x70090', '0x180000') +('CURAPALET1', '0x70094', '0x180000') +('CURAPALET2', '0x70098', '0x180000') +('CURAPALET3', '0x7009C', '0x180000') +('CURALIVEBASE', '0x700AC', '0x180000') + +('SPACNTR', '0x72180', '0x180000') +('SPALINOFF', '0x72184', '0x180000') +('SPASTRIDE', '0x72188', '0x180000') +('SPAPOS', '0x7218C', '0x180000') +('SPASIZE', '0x72190', '0x180000') +('SPAKEYMINVAL', '0x72194', '0x180000') +('SPAKEYMSK', '0x72198', '0x180000') +('SPASURF', '0x7219C', '0x180000') +('SPAKEYMAXVAL', '0x721A0', '0x180000') +('SPATILEOFF', '0x721A4', '0x180000') +('SPACONTALPHA', '0x721A8', '0x180000') +('SPALIVESURF', '0x721AC', '0x180000') +('SPACLRC0', '0x721D0', '0x180000') +('SPACLRC1', '0x721D4', '0x180000') +('SPAGAMC5', '0x721E0', '0x180000') +('SPAGAMC4', '0x721E4', '0x180000') +('SPAGAMC3', '0x721E8', '0x180000') +('SPAGAMC2', '0x721EC', '0x180000') +('SPAGAMC1', '0x721F0', '0x180000') +('SPAGAMC0', '0x721F4', '0x180000') + +('SPBCNTR', '0x72280', '0x180000') +('SPBLINOFF', '0x72284', '0x180000') +('SPBSTRIDE', '0x72288', '0x180000') +('SPBPOS', '0x7228C', '0x180000') +('SPBSIZE', '0x72290', '0x180000') +('SPBKEYMINVAL', '0x72294', '0x180000') +('SPBKEYMSK', '0x72298', '0x180000') +('SPBSURF', '0x7229C', '0x180000') +('SPBKEYMAXVAL', '0x722A0', '0x180000') +('SPBTILEOFF', '0x722A4', '0x180000') +('SPBCONTALPHA', '0x722A8', '0x180000') +('SPBLIVESURF', '0x722AC', '0x180000') +('SPBCLRC0', '0x722D0', '0x180000') +('SPBCLRC1', '0x722D4', '0x180000') +('SPBGAMC5', '0x722E0', '0x180000') +('SPBGAMC4', '0x722E4', '0x180000') +('SPBGAMC3', '0x722E8', '0x180000') +('SPBGAMC2', '0x722EC', '0x180000') +('SPBGAMC1', '0x722F0', '0x180000') +('SPBGAMC0', '0x722F4', '0x180000') + +('DPALETTE_A', '0xA000', '0x180000') +('DPLLA_CTRL', '0x6014', '0x180000') +('DPLLAMD', '0x601C', '0x180000') + +('HTOTAL_A', '0x60000', '0x180000') +('HBLANK_A', '0x60004', '0x180000') +('HSYNC_A', '0x60008', '0x180000') +('VTOTAL_A', '0x6000C', '0x180000') +('VBLANK_A', '0x60010', '0x180000') +('VSYNC_A', '0x60014', '0x180000') +('PIPESRCA', '0x6001C', '0x180000') +('BCLRPAT_A', '0x60020', '0x180000') +('VSYNCSHIFT_A', '0x60028', '0x180000') + +('TRANSA_DATA_M1', '0x60030', '0x180000') +('TRANSA_DATA_N1', '0x60034', '0x180000') +('TRANSA_DATA_M2', '0x60038', '0x180000') +('TRANSA_DATA_N2', '0x6003C', '0x180000') +('TRANSA_LINK_M1', '0x60040', '0x180000') +('TRANSA_LINK_N1', '0x60044', '0x180000') +('TRANSA_LINK_M2', '0x60048', '0x180000') +('TRANSA_LINK_N2', '0x6004C', '0x180000') + +('CRC_CTRL_RED_A', '0x60050', '0x180000') +('CRC_CTRL_GREEN_A', '0x60054', '0x180000') +('CRC_CTRL_BLUE_A', '0x60058', '0x180000') +('CRC_CTRL_ALPHA_A', '0x6005C', '0x180000') +('CRC_CTRL_RESIDUE2_A', '0x60070', '0x180000') +('CRC_RES_RED_A', '0x60060', '0x180000') +('CRC_RES_GREEN_A', '0x60064', '0x180000') +('CRC_RES_BLUE_A', '0x60068', '0x180000') +('CRC_RES_ALPHA_A', '0x6006C', '0x180000') +('CRC_RES_RESIDUE2_A', '0x60080', '0x180000') + +('PSRCTLA', '0x60090', '0x180000') +('PSRSTATA', '0x60094', '0x180000') +('PSRCRC1A', '0x60098', '0x180000') +('PSRCRC2A', '0x6009C', '0x180000') +('VSCSDPA', '0x600A0', '0x180000') + +('PIPEA_WGCC_C01_C00', '0x600B0', '0x180000') +('PIPEA_WGCC_C02', '0x600B4', '0x180000') +('PIPEA_WGCC_C11_C10', '0x600B8', '0x180000') +('PIPEA_WGCC_C12', '0x600BC', '0x180000') +('PIPEA_WGCC_C21_C20', '0x600C0', '0x180000') +('PIPEA_WGCC_C22', '0x600C4', '0x180000') + +('VIDEO_DIP_CTL_A', '0x60200', '0x180000') +('VIDEO_DIP_DATA_A', '0x60208', '0x180000') +('VIDEO_DIP_GDCP_PAYLOAD_A', '0x60210', '0x180000') + +('PIPEA_CGM_DEGAMMA', '0x66000', '0x180000') +('PIPEA_CGM_GAMMA', '0x67000', '0x180000') +('PIPEA_CGM_CSC_COEFF01', '0x67900', '0x180000') +('PIPEA_CGM_CSC_COEFF23', '0x67904', '0x180000') +('PIPEA_CGM_CSC_COEFF45', '0x67908', '0x180000') +('PIPEA_CGM_CSC_COEFF67', '0x6790C', '0x180000') +('PIPEA_CGM_CSC_COEFF8', '0x67910', '0x180000') +('PIPEA_CGM_CONTROL', '0x67A00', '0x180000') + +('PIPEA_PP_STATUS', '0x61200', '0x180000') +('PIPEA_PP_CONTROL', '0x61204', '0x180000') +('PIPEA_PP_ON_DELAYS', '0x61208', '0x180000') +('PIPEA_PP_OFF_DELAYS', '0x6120C', '0x180000') +('PIPEA_PP_DIVISOR', '0x61210', '0x180000') + +('PIPEA_BLC_PWM_CLT2', '0x61250', '0x180000') +('PIPEA_BLC_PWM_CTL', '0x61254', '0x180000') +('PIPEA_BLM_HIST_CTL', '0x61260', '0x180000') +('PIPEA_IMG_ENH_BIN_DATA', '0x61264', '0x180000') +('PIPEA_HIST_THRESH_GUARD', '0x61268', '0x180000') + +('AUD_CONFIG_A', '0x62000', '0x180000') +('AUD_MISC_CTRL_A', '0x62010', '0x180000') +('AUD_CTS_ENABLE_A', '0x62028', '0x180000') +('AUD_HDMIW_HDMIEDID_A', '0x62050', '0x180000') +('AUD_HDMIW_INFOFR_A', '0x62054', '0x180000') +('AUD_OUT_DIG_CNVT_A', '0x62080', '0x180000') +('AUD_OUT_STR_DESC_A', '0x62084', '0x180000') +('AUD_CNTL_ST_A', '0x620B4', '0x180000') +('AUD_OUT_STR_DESC_A_DBG', '0x62F08', '0x180000') +('AUD_OUT_DIG_CNVTA_DBG', '0x62F40', '0x180000') + +('STREAM_A_LPE_AUD_CONFIG', '0x65000', '0x180000') +('STREAM_A_LPE_AUD_CH_STATUS_0', '0x65008', '0x180000') +('STREAM_A_LPE_AUD_CH_STATUS_1', '0x6500C', '0x180000') +('STREAM_A_LPE_AUD_HDMI_CTS_DP_MAUD', '0x65010', '0x180000') +('STREAM_A_LPE_AUD_HDMI_N_DP_NAUD', '0x65014', '0x180000') +('STREAM_A_LPE_AUD_BUFFER_CONFIG', '0x65020', '0x180000') +('STREAM_A_LPE_AUD_BUF_CH_SWP', '0x65024', '0x180000') +('STREAM_A_LPE_AUD_BUF_A_ADDR', '0x65040', '0x180000') +('STREAM_A_LPE_AUD_BUF_A_LENGTH', '0x65044', '0x180000') +('STREAM_A_LPE_AUD_BUF_B_ADDR', '0x65048', '0x180000') +('STREAM_A_LPE_AUD_BUF_B_LENGTH', '0x6504C', '0x180000') +('STREAM_A_LPE_AUD_BUF_C_ADDR', '0x65050', '0x180000') +('STREAM_A_LPE_AUD_BUF_C_LENGTH', '0x65054', '0x180000') +('STREAM_A_LPE_AUD_BUF_D_ADDR', '0x65058', '0x180000') +('STREAM_A_LPE_AUD_BUF_D_LENGTH', '0x6505C', '0x180000') +('STREAM_A_LPE_AUD_CNTL_ST', '0x65060', '0x180000') +('STREAM_A_LPE_AUD_HDMI_STATUS', '0x65064', '0x180000') +('STREAM_A_LPE_AUD_HDMIW_INFOFR', '0x65068', '0x180000') diff --git a/tools/registers/vlv_pipe_b.txt b/tools/registers/vlv_pipe_b.txt new file mode 100644 index 00000000..de5e9681 --- /dev/null +++ b/tools/registers/vlv_pipe_b.txt @@ -0,0 +1,174 @@ +('PIPEB_DSL', '0x71000', '0x180000') +('PIPEB_SLC', '0x71004', '0x180000') +('PIPEBCONF', '0x71008', '0x180000') +('PIPEBGCMAXRED', '0x71010', '0x180000') +('PIPEBGCMAXGREEN', '0x71014', '0x180000') +('PIPEBGCMAXBLUE', '0x71018', '0x180000') +('PIPEBSTAT', '0x71024', '0x180000') +('PIPEBFRAMECOUNT', '0x71040', '0x180000') +('PIPEBFLIPCOUNT', '0x71044', '0x180000') +('PIPEBMSAMISC', '0x71048', '0x180000') + +('DSPBADDR', '0x7117C', '0x180000') +('DSPBCNTR', '0x71180', '0x180000') +('DSPBLINOFF', '0x71184', '0x180000') +('DSPBSTRIDE', '0x71188', '0x180000') +('DSPBKEYVAL', '0x71194', '0x180000') +('DSPBKEYMSK', '0x71198', '0x180000') +('DSPBSURF', '0x7119C', '0x180000') +('DSPBTILEOFF', '0x711A4', '0x180000') +('DSPBSURFLIVE', '0x711AC', '0x180000') +('DSPBFLPQSTAT', '0x71200', '0x180000') + +('CURBCNTR', '0x700C0', '0x180000') +('CURBBASE', '0x700C4', '0x180000') +('CURBPOS', '0x700C8', '0x180000') +('CURBRESV', '0x700CC', '0x180000') +('CURBPALET0', '0x700D0', '0x180000') +('CURBPALET1', '0x700D4', '0x180000') +('CURBPALET2', '0x700D8', '0x180000') +('CURBPALET3', '0x700DC', '0x180000') +('CURBLIVEBASE', '0x700EC', '0x180000') + +('SPCCNTR', '0x72380', '0x180000') +('SPCLINOFF', '0x72384', '0x180000') +('SPCSTRIDE', '0x72388', '0x180000') +('SPCPOS', '0x7238C', '0x180000') +('SPCSIZE', '0x72390', '0x180000') +('SPCKEYMINVAL', '0x72394', '0x180000') +('SPCKEYMSK', '0x72398', '0x180000') +('SPCSURF', '0x7239C', '0x180000') +('SPCKEYMAXVAL', '0x723A0', '0x180000') +('SPCTILEOFF', '0x723A4', '0x180000') +('SPCCONTALPHA', '0x723A8', '0x180000') +('SPCLIVESURF', '0x723AC', '0x180000') +('SPCCLRC0', '0x723D0', '0x180000') +('SPCCLRC1', '0x723D4', '0x180000') +('SPCGAMC5', '0x723E0', '0x180000') +('SPCGAMC4', '0x723E4', '0x180000') +('SPCGAMC3', '0x723E8', '0x180000') +('SPCGAMC2', '0x723EC', '0x180000') +('SPCGAMC1', '0x723F0', '0x180000') +('SPCGAMC0', '0x723F4', '0x180000') + +('SPDCNTR', '0x72480', '0x180000') +('SPDLINOFF', '0x72484', '0x180000') +('SPDSTRIDE', '0x72488', '0x180000') +('SPDPOS', '0x7248C', '0x180000') +('SPDSIZE', '0x72490', '0x180000') +('SPDKEYMINVAL', '0x72494', '0x180000') +('SPDKEYMSK', '0x72498', '0x180000') +('SPDSURF', '0x7249C', '0x180000') +('SPDKEYMAXVAL', '0x724A0', '0x180000') +('SPDTILEOFF', '0x724A4', '0x180000') +('SPDCONTALPHA', '0x724A8', '0x180000') +('SPDLIVESURF', '0x724AC', '0x180000') +('SPDCLRC0', '0x724D0', '0x180000') +('SPDCLRC1', '0x724D4', '0x180000') +('SPDGAMC5', '0x724E0', '0x180000') +('SPDGAMC4', '0x724E4', '0x180000') +('SPDGAMC3', '0x724E8', '0x180000') +('SPDGAMC2', '0x724EC', '0x180000') +('SPDGAMC1', '0x724F0', '0x180000') +('SPDGAMC0', '0x724F4', '0x180000') + +('DPALETTE_B', '0xA800', '0x180000') +('DPLLB_CTRL', '0x6018', '0x180000') +('DPLLBMD', '0x6020', '0x180000') + +('HTOTAL_B', '0x61000', '0x180000') +('HBLANK_B', '0x61004', '0x180000') +('HSYNC_B', '0x61008', '0x180000') +('VTOTAL_B', '0x6100C', '0x180000') +('VBLANK_B', '0x61010', '0x180000') +('VSYNC_B', '0x61014', '0x180000') +('PIPEBSRC', '0x6101C', '0x180000') +('BCLRPAT_B', '0x61020', '0x180000') +('VSYNCSHIFT_B', '0x61028', '0x180000') + +('TRANSB_DATA_M1', '0x61030', '0x180000') +('TRANSB_DATA_N1', '0x61034', '0x180000') +('TRANSB_DATA_M2', '0x61038', '0x180000') +('TRANSB_DATA_N2', '0x6103C', '0x180000') +('TRANSB_LINK_M1', '0x61040', '0x180000') +('TRANSB_LINK_N1', '0x61044', '0x180000') +('TRANSB_LINK_M2', '0x61048', '0x180000') +('TRANSB_LINK_N2', '0x6104C', '0x180000') + +('CRC_CTRL_RED_B', '0x61050', '0x180000') +('CRC_CTRL_GREEN_B', '0x61054', '0x180000') +('CRC_CTRL_BLUE_B', '0x61058', '0x180000') +('CRC_CTRL_ALPHA_B', '0x6105C', '0x180000') +('CRC_CTRL_RESIDUE2_B', '0x61070', '0x180000') +('CRC_RES_RED_B', '0x61060', '0x180000') +('CRC_RES_GREEN_B', '0x61064', '0x180000') +('CRC_RES_BLUE_V', '0x61068', '0x180000') +('CRC_RES_ALPHAB', '0x6106C', '0x180000') +('CRC_RES_RESIDUAL2_B', '0x61080', '0x180000') + +('PSRCTLB', '0x61090', '0x180000') +('PSRSTATB', '0x61094', '0x180000') +('PSRCRC1B', '0x61098', '0x180000') +('PSRCRC2B', '0x6109C', '0x180000') +('VSCSDPB', '0x610A0', '0x180000') + +('PIPEB_WGCC_C01_C00', '0x610B0', '0x180000') +('PIPEB_WGCC_C02', '0x610B4', '0x180000') +('PIPEB_WGCC_C11_C10', '0x610B8', '0x180000') +('PIPEB_WGCC_C12', '0x610BC', '0x180000') +('PIPEB_WGCC_C21_C20', '0x610C0', '0x180000') +('PIPEB_WGCC_C22', '0x610C4', '0x180000') + +('VIDEO_DIP_CTL_B', '0x61170', '0x180000') +('VIDEO_DIP_DATA_B', '0x61174', '0x180000') +('VIDEO_DIP_GDCP_PAYLOAD_B', '0x61178', '0x180000') + +('PIPEB_CGM_DEGAMMA', '0x68000', '0x180000') +('PIPEB_CGM_GAMMA', '0x69000', '0x180000') +('PIPEB_CGM_CSC_COEFF01', '0x69900', '0x180000') +('PIPEB_CGM_CSC_COEFF23', '0x69904', '0x180000') +('PIPEB_CGM_CSC_COEFF45', '0x69908', '0x180000') +('PIPEB_CGM_CSC_COEFF67', '0x6990C', '0x180000') +('PIPEB_CGM_CSC_COEFF8', '0x69910', '0x180000') +('PIPEB_CGM_CONTROL', '0x69A00', '0x180000') + +('PIPEB_PP_STATUS', '0x61300', '0x180000') +('PIPEB_PP_CONTROL', '0x61304', '0x180000') +('PIPEB_PP_ON_DELAYS', '0x61308', '0x180000') +('PIPEB_PP_OFF_DELAYS', '0x6130C', '0x180000') +('PIPEB_PP_DIVISOR', '0x61310', '0x180000') + +('PIPEB_BLC_PWM_CLT2', '0x61350', '0x180000') +('PIPEB_BLC_PWM_CTL', '0x61354', '0x180000') +('PIPEB_BLM_HIST_CTL', '0x61360', '0x180000') +('PIPEB_IMG_ENH_BIN_DATA', '0x61364', '0x180000') +('PIPEB_HIST_THRESH_GUARD', '0x61368', '0x180000') + +('AUD_CONFIG_B', '0x62100', '0x180000') +('AUD_MISC_CTRL_B', '0x62110', '0x180000') +('AUD_CTS_ENABLE_B', '0x62128', '0x180000') +('AUD_HDMIW_HDMIEDID_B', '0x62150', '0x180000') +('AUD_HDMIW_INFOFR_B', '0x62154', '0x180000') +('AUD_OUT_DIG_CNVT_B', '0x62180', '0x180000') +('AUD_OUT_STR_DESC_B', '0x62184', '0x180000') +('AUD_CNTL_ST_B', '0x621B4', '0x180000') +('AUD_OUT_DIG_CNVTB_DBG', '0x62F44', '0x180000') + +('STREAM_B_LPE_AUD_CONFIG', '0x65800', '0x180000') +('STREAM_B_LPE_AUD_CH_STATUS_0', '0x65808', '0x180000') +('STREAM_B_LPE_AUD_CH_STATUS_1', '0x6580C', '0x180000') +('STREAM_B_LPE_AUD_HDMI_CTS_DP_MAUD', '0x65810', '0x180000') +('STREAM_B_LPE_AUD_HDMI_N_DP_NAUD', '0x65814', '0x180000') +('STREAM_B_LPE_AUD_BUFFER_CONFIG', '0x65820', '0x180000') +('STREAM_B_LPE_AUD_BUF_CH_SWP', '0x65824', '0x180000') +('STREAM_B_LPE_AUD_BUF_A_ADDR', '0x65840', '0x180000') +('STREAM_B_LPE_AUD_BUF_A_LENGTH', '0x65844', '0x180000') +('STREAM_B_LPE_AUD_BUF_B_ADDR', '0x65848', '0x180000') +('STREAM_B_LPE_AUD_BUF_B_LENGTH', '0x6584C', '0x180000') +('STREAM_B_LPE_AUD_BUF_C_ADDR', '0x65850', '0x180000') +('STREAM_B_LPE_AUD_BUF_C_LENGTH', '0x65854', '0x180000') +('STREAM_B_LPE_AUD_BUF_D_ADDR', '0x65858', '0x180000') +('STREAM_B_LPE_AUD_BUF_D_LENGTH', '0x6585C', '0x180000') +('STREAM_B_LPE_AUD_CNTL_ST', '0x65860', '0x180000') +('STREAM_B_LPE_AUD_HDMI_STATUS', '0x65864', '0x180000') +('STREAM_B_LPE_AUD_HDMIW_INFOFR', '0x65868', '0x180000') diff --git a/tools/registers/vlv_power.txt b/tools/registers/vlv_power.txt new file mode 100644 index 00000000..afb83e81 --- /dev/null +++ b/tools/registers/vlv_power.txt @@ -0,0 +1,14 @@ +('GTLC wake control', '0x130090', '') +('GTLC power well status', '0x130094', '') +('Render forcewake req', '0x1300b0', '') +('Render forcewake ack', '0x1300b4', '') +('Counter control', '0x138104', '') +('RC6 counter', '0x138108', '') +('RC6_SLEEP', 0xa0b0, '') +('RC6_WAKE_LIMIT', 0xa09c, '') +('RC_EI', 0xa0a8, '') +('RC_IDLE_HYSTERESIS', 0xa0ac, '') +('RC6_THRESHOLD', 0xa0b8, '') +('RC6p_THRESHOLD', 0xa0bc, '') +('RC6pp_THRESHOLD', 0xa0c0, '') +('RC_CONTROL', 0xa090, '') |