intel_chipset: Replace lookup of GT size with computation

Instead of a large if-chain for matching devid to GT, we can just
compute it directly from the encoded devid.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

2 files changed, 16 insertions, 18 deletions

diff --git a/tools/intel_l3_parity.c b/tools/intel_l3_parity.c
index 4810f7a9..ecc0c613 100644
--- a/tools/intel_l3_parity.c
+++ b/tools/intel_l3_parity.c
@@ -51,14 +51,11 @@ static unsigned int devid;
 /* L3 size is always a function of banks. The number of banks cannot be
  * determined by number of slices however */
 static inline int num_banks(void) {
-	if (IS_HSW_GT3(devid))
-		return 8; /* 4 per each slice */
-	else if (IS_HSW_GT1(devid) ||
-			devid == PCI_CHIP_IVYBRIDGE_GT1 ||
-			devid == PCI_CHIP_IVYBRIDGE_M_GT1)
-		return 2;
-	else
-		return 4;
+	switch (intel_gt(devid)) {
+	case 2: return 8;
+	case 1: return 4;
+	default: return 2;
+	}
 }
 #define NUM_SUBBANKS 8
 #define BYTES_PER_BANK (128 << 10)
@@ -68,7 +65,7 @@ static inline int num_banks(void) {
 #define MAX_ROW (1<<12)
 #define MAX_BANKS_PER_SLICE 4
 #define NUM_REGS (MAX_BANKS_PER_SLICE * NUM_SUBBANKS)
-#define MAX_SLICES (IS_HSW_GT3(devid) ? 2 : 1)
+#define MAX_SLICES (intel_gt(devid) > 1 ? 2 : 1)
 #define REAL_MAX_SLICES 2
 /* TODO support SLM config */
 #define L3_SIZE ((MAX_ROW * 4) * NUM_SUBBANKS *  num_banks())
diff --git a/tools/intel_reg_checker.c b/tools/intel_reg_checker.c
index 2d6da70c..6bde63ec 100644
--- a/tools/intel_reg_checker.c
+++ b/tools/intel_reg_checker.c
@@ -162,16 +162,17 @@ check_gt_mode(void)
 	if (gen == 6)
 		check_perf_bit(gt_mode, 8, "Full Rate Sampler Disable", false);
 
-	/* For DevSmallGT, this bit must be set, which means disable
-	 * hashing.
-	 */
-	if (devid == PCI_CHIP_SANDYBRIDGE_GT1 ||
-	    devid == PCI_CHIP_SANDYBRIDGE_M_GT1)
-		check_bit(gt_mode, 6, "WIZ Hashing disable", true);
-	else if (gen == 6)
-		check_perf_bit(gt_mode, 6, "WIZ Hashing disable", false);
-
 	if (gen == 6) {
+		/* For DevSmallGT, this bit must be set, which means disable
+		 * hashing.
+		 */
+		if (intel_gt(devid) == 0)
+			check_bit(gt_mode, 6,
+				  "WIZ Hashing disable", true);
+		else
+			check_perf_bit(gt_mode, 6,
+				       "WIZ Hashing disable", false);
+
 		check_perf_bit(gt_mode, 5, "TD Four Row Dispatch Disable",
 			       false);
 		check_perf_bit(gt_mode, 4, "Full Size URB Disable", false);