lib/rendercopy: Use gen4 definitions if applicable

Instead of using definitions duplicated in gen7_render header,
we should use the oldest definition that is working with chosen
gen. This patch reuse gen6 definitons if registers/fields/shifts
that were introduced in other genX_render headers.

v3: Rebase and checkpatch

Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>

4 files changed, 114 insertions, 114 deletions

diff --git a/tools/null_state_gen/intel_renderstate_gen6.c b/tools/null_state_gen/intel_renderstate_gen6.c
index 13b1e92e..c779ea42 100644
--- a/tools/null_state_gen/intel_renderstate_gen6.c
+++ b/tools/null_state_gen/intel_renderstate_gen6.c
@@ -81,7 +81,7 @@ gen6_bind_surfaces(struct intel_batchbuffer *batch)
 static void
 gen6_emit_sip(struct intel_batchbuffer *batch)
 {
-	OUT_BATCH(GEN6_STATE_SIP | 0);
+	OUT_BATCH(GEN4_STATE_SIP | 0);
 	OUT_BATCH(0);
 }
 
@@ -98,7 +98,7 @@ gen6_emit_urb(struct intel_batchbuffer *batch)
 static void
 gen6_emit_state_base_address(struct intel_batchbuffer *batch)
 {
-	OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
+	OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2));
 	OUT_BATCH(0); /* general */
 	OUT_RELOC(batch,
 		  I915_GEM_DOMAIN_INSTRUCTION, 0,
@@ -189,23 +189,23 @@ gen6_emit_wm_constants(struct intel_batchbuffer *batch)
 static void
 gen6_emit_null_depth_buffer(struct intel_batchbuffer *batch)
 {
-	OUT_BATCH(GEN6_3DSTATE_DEPTH_BUFFER | (7 - 2));
-	OUT_BATCH(SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
-		  GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
+	OUT_BATCH(GEN4_3DSTATE_DEPTH_BUFFER | (7 - 2));
+	OUT_BATCH(SURFACE_NULL << GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
+		  GEN4_DEPTHFORMAT_D32_FLOAT << GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 
-	OUT_BATCH(GEN6_3DSTATE_CLEAR_PARAMS | (2 - 2));
+	OUT_BATCH(GEN4_3DSTATE_CLEAR_PARAMS | (2 - 2));
 	OUT_BATCH(0);
 }
 
 static void
 gen6_emit_invariant(struct intel_batchbuffer *batch)
 {
-	OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+	OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 
 	OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
 	OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
@@ -284,7 +284,7 @@ gen6_emit_wm(struct intel_batchbuffer *batch, int kernel)
 static void
 gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table)
 {
-	OUT_BATCH(GEN6_3DSTATE_BINDING_TABLE_POINTERS |
+	OUT_BATCH(GEN4_3DSTATE_BINDING_TABLE_POINTERS |
 		  GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
 		  (4 - 2));
 	OUT_BATCH(0);		/* vs */
@@ -295,7 +295,7 @@ gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table)
 static void
 gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch)
 {
-	OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+	OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
 	OUT_BATCH(0xffffffff);
 	OUT_BATCH(0 | 0);
 	OUT_BATCH(0);
@@ -311,39 +311,39 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch)
 	 *
 	 * dword 4-11 are fetched from vertex buffer
 	 */
-	OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2));
+	OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2));
 
-	OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+	OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
 		  SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
 		  0 << VE0_OFFSET_SHIFT);
-	OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+	OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
 
 	/* x,y */
-	OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+	OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
 		  SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
 		  0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
-	OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+	OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
 
 	/* u0, v0 */
-	OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+	OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
 		  SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
 		  4 << VE0_OFFSET_SHIFT);	/* offset vb in bytes */
-	OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+	OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
 }
 
 static uint32_t
 gen6_create_cc_viewport(struct intel_batchbuffer *batch)
 {
-	struct gen6_cc_viewport vp;
+	struct gen4_cc_viewport vp;
 
 	memset(&vp, 0, sizeof(vp));
 
@@ -392,41 +392,41 @@ gen6_create_sampler(struct intel_batchbuffer *batch,
 
 	/* We use the legacy mode to get the semantics specified by
 	 * the Render extension. */
-	ss.ss0.border_color_mode = GEN6_BORDER_COLOR_MODE_LEGACY;
+	ss.ss0.border_color_mode = GEN4_BORDER_COLOR_MODE_LEGACY;
 
 	switch (filter) {
 	default:
 	case SAMPLER_FILTER_NEAREST:
-		ss.ss0.min_filter = GEN6_MAPFILTER_NEAREST;
-		ss.ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
+		ss.ss0.min_filter = GEN4_MAPFILTER_NEAREST;
+		ss.ss0.mag_filter = GEN4_MAPFILTER_NEAREST;
 		break;
 	case SAMPLER_FILTER_BILINEAR:
-		ss.ss0.min_filter = GEN6_MAPFILTER_LINEAR;
-		ss.ss0.mag_filter = GEN6_MAPFILTER_LINEAR;
+		ss.ss0.min_filter = GEN4_MAPFILTER_LINEAR;
+		ss.ss0.mag_filter = GEN4_MAPFILTER_LINEAR;
 		break;
 	}
 
 	switch (extend) {
 	default:
 	case SAMPLER_EXTEND_NONE:
-		ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
-		ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
-		ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
+		ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
+		ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
+		ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
 		break;
 	case SAMPLER_EXTEND_REPEAT:
-		ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
-		ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
-		ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
+		ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
+		ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
+		ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
 		break;
 	case SAMPLER_EXTEND_PAD:
-		ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
-		ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
-		ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+		ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+		ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+		ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
 		break;
 	case SAMPLER_EXTEND_REFLECT:
-		ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
-		ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
-		ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
+		ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
+		ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
+		ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
 		break;
 	}
 
@@ -450,9 +450,9 @@ static void gen6_emit_vertex_buffer(struct intel_batchbuffer *batch)
 
 	offset = gen6_create_vertex_buffer(batch);
 
-	OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | 3);
-	OUT_BATCH(VB0_VERTEXDATA |
-		  0 << VB0_BUFFER_INDEX_SHIFT |
+	OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | 3);
+	OUT_BATCH(GEN6_VB0_VERTEXDATA |
+		  0 << GEN6_VB0_BUFFER_INDEX_SHIFT |
 		  VB0_NULL_VERTEX_BUFFER |
 		  0 << VB0_BUFFER_PITCH_SHIFT);
 	OUT_RELOC_STATE(batch, I915_GEM_DOMAIN_VERTEX, 0, offset);
diff --git a/tools/null_state_gen/intel_renderstate_gen7.c b/tools/null_state_gen/intel_renderstate_gen7.c
index 75ee9d6d..519ad30a 100644
--- a/tools/null_state_gen/intel_renderstate_gen7.c
+++ b/tools/null_state_gen/intel_renderstate_gen7.c
@@ -49,36 +49,36 @@ gen7_bind_buf_null(struct intel_batchbuffer *batch)
 static void
 gen7_emit_vertex_elements(struct intel_batchbuffer *batch)
 {
-	OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS |
+	OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS |
 		  ((2 * (1 + 2)) + 1 - 2));
 
-	OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+	OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
 		  SURFACEFORMAT_R32G32B32A32_FLOAT <<
 		  VE0_FORMAT_SHIFT |
 		  0 << VE0_OFFSET_SHIFT);
 
-	OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+	OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
 
 	/* x,y */
-	OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+	OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
 		  SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
 		  0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
-	OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+	OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
 
 	/* s,t */
-	OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+	OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
 		  SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
 		  4 << VE0_OFFSET_SHIFT);  /* offset vb in bytes */
-	OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
-		  GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+	OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+		  GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
 }
 
 static uint32_t
@@ -95,9 +95,9 @@ static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch)
 
 	offset = gen7_create_vertex_buffer(batch);
 
-	OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (5 - 2));
-	OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT |
-		  VB0_VERTEXDATA |
+	OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (5 - 2));
+	OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT |
+		  GEN6_VB0_VERTEXDATA |
 		  GEN7_VB0_ADDRESS_MODIFY_ENABLE |
 		  VB0_NULL_VERTEX_BUFFER |
 		  4*2 << VB0_BUFFER_PITCH_SHIFT);
@@ -130,7 +130,7 @@ gen7_emit_binding_table(struct intel_batchbuffer *batch)
 static void
 gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch)
 {
-	OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+	OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
 	/* Purposedly set min > max for null rectangle */
 	OUT_BATCH(0xffffffff);
 	OUT_BATCH(0 | 0);
@@ -155,7 +155,7 @@ gen7_create_blend_state(struct intel_batchbuffer *batch)
 static void
 gen7_emit_state_base_address(struct intel_batchbuffer *batch)
 {
-	OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
+	OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2));
 	OUT_BATCH(0);
 	OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
 	OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
@@ -171,7 +171,7 @@ gen7_emit_state_base_address(struct intel_batchbuffer *batch)
 static uint32_t
 gen7_create_cc_viewport(struct intel_batchbuffer *batch)
 {
-	struct gen6_cc_viewport vp;
+	struct gen4_cc_viewport vp;
 	memset(&vp, 0, sizeof(vp));
 
 	vp.min_depth = -1.e35;
@@ -196,12 +196,12 @@ gen7_create_sampler(struct intel_batchbuffer *batch)
 	struct gen7_sampler_state ss;
 	memset(&ss, 0, sizeof(ss));
 
-	ss.ss0.min_filter = GEN6_MAPFILTER_NEAREST;
-	ss.ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
+	ss.ss0.min_filter = GEN4_MAPFILTER_NEAREST;
+	ss.ss0.mag_filter = GEN4_MAPFILTER_NEAREST;
 
-	ss.ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
-	ss.ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
-	ss.ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+	ss.ss3.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+	ss.ss3.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+	ss.ss3.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
 
 	ss.ss3.non_normalized_coord = 1;
 
@@ -402,7 +402,7 @@ gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch)
 {
 	OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
 	OUT_BATCH(SURFACE_NULL << GEN7_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
-		  GEN6_DEPTHFORMAT_D32_FLOAT <<
+		  GEN4_DEPTHFORMAT_D32_FLOAT <<
 		  GEN7_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
 	OUT_BATCH(0); /* disable depth, stencil and hiz */
 	OUT_BATCH(0);
@@ -417,7 +417,7 @@ gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch)
 
 void gen7_setup_null_render_state(struct intel_batchbuffer *batch)
 {
-	OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+	OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 
 	gen7_emit_state_base_address(batch);
 	gen7_emit_multisample(batch);
@@ -442,8 +442,8 @@ void gen7_setup_null_render_state(struct intel_batchbuffer *batch)
 	gen7_emit_binding_table(batch);
 	gen7_emit_drawing_rectangle(batch);
 
-	OUT_BATCH(GEN6_3DPRIMITIVE | (7 - 2));
-	OUT_BATCH(GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
+	OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2));
+	OUT_BATCH(GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
 	OUT_BATCH(3);
 	OUT_BATCH(0);
 	OUT_BATCH(1);   /* single instance */
diff --git a/tools/null_state_gen/intel_renderstate_gen8.c b/tools/null_state_gen/intel_renderstate_gen8.c
index c6973e0e..17822c44 100644
--- a/tools/null_state_gen/intel_renderstate_gen8.c
+++ b/tools/null_state_gen/intel_renderstate_gen8.c
@@ -152,7 +152,7 @@ static void gen8_emit_so_buffer(struct intel_batchbuffer *batch, const int index
 
 static void gen8_emit_state_base_address(struct intel_batchbuffer *batch) {
 	const unsigned offset = 0;
-	OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (16 - 2));
+	OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (16 - 2));
 
 	/* general */
 	OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
@@ -200,10 +200,10 @@ static void gen8_emit_vertex_buffers(struct intel_batchbuffer *batch)
 	const int buffers = 33;
 	int i;
 
-	OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | ((4 * buffers) - 1));
+	OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | ((4 * buffers) - 1));
 
 	for (i = 0; i < buffers; i++) {
-		OUT_BATCH(i << VB0_BUFFER_INDEX_SHIFT |
+		OUT_BATCH(i << GEN6_VB0_BUFFER_INDEX_SHIFT |
 			  GEN8_VB0_BUFFER_ADDR_MOD_EN);
 		OUT_BATCH(0); /* Addr */
 		OUT_BATCH(0);
@@ -216,16 +216,16 @@ static void gen6_emit_vertex_elements(struct intel_batchbuffer *batch)
 	const int elements = 34;
 	int i;
 
-	OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | ((2 * elements - 1)));
+	OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | ((2 * elements - 1)));
 
 	for (i = 0; i < elements; i++) {
 		if (i == 0) {
-			OUT_BATCH(VE0_VALID | i);
+			OUT_BATCH(GEN6_VE0_VALID | i);
 			OUT_BATCH(
-				GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
-				GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
-				GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
-				GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT
+				GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+				GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+				GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+				GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT
 				);
 		} else {
 			OUT_BATCH(0);
@@ -314,13 +314,13 @@ static void gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer *
 
 static void gen8_emit_primitive(struct intel_batchbuffer *batch)
 {
-        OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
-        OUT_BATCH(4);   /* gen8+ ignore the topology type field */
-        OUT_BATCH(1);   /* vertex count */
-        OUT_BATCH(0);
-        OUT_BATCH(1);   /* single instance */
-        OUT_BATCH(0);   /* start instance location */
-        OUT_BATCH(0);   /* index buffer offset, ignored */
+	OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2));
+	OUT_BATCH(4);   /* gen8+ ignore the topology type field */
+	OUT_BATCH(1);   /* vertex count */
+	OUT_BATCH(0);
+	OUT_BATCH(1);   /* single instance */
+	OUT_BATCH(0);   /* start instance location */
+	OUT_BATCH(0);   /* index buffer offset, ignored */
 }
 
 void gen8_setup_null_render_state(struct intel_batchbuffer *batch)
@@ -334,7 +334,7 @@ void gen8_setup_null_render_state(struct intel_batchbuffer *batch)
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 
-	OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+	OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 
 	gen8_emit_wm(batch);
 	gen8_emit_ps(batch);
@@ -383,8 +383,8 @@ void gen8_setup_null_render_state(struct intel_batchbuffer *batch)
 
 	gen8_emit_state_base_address(batch);
 
-	OUT_CMD(GEN6_STATE_SIP, 3);
-	OUT_CMD(GEN6_3DSTATE_DRAWING_RECTANGLE, 4);
+	OUT_CMD(GEN4_STATE_SIP, 3);
+	OUT_CMD(GEN4_3DSTATE_DRAWING_RECTANGLE, 4);
 	OUT_CMD(GEN7_3DSTATE_DEPTH_BUFFER, 8);
 
 	gen8_emit_chroma_key(batch, 0);
diff --git a/tools/null_state_gen/intel_renderstate_gen9.c b/tools/null_state_gen/intel_renderstate_gen9.c
index 9f338bbf..3701acd1 100644
--- a/tools/null_state_gen/intel_renderstate_gen9.c
+++ b/tools/null_state_gen/intel_renderstate_gen9.c
@@ -163,11 +163,11 @@ static void gen8_emit_vertex_buffers(struct intel_batchbuffer *batch)
 	const int buffers = 33;
 	int i;
 
-	OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS |
+	OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS |
 		(((4 * buffers) + 1)- 2) /* DWORD count - 2 */);
 
 	for (i = 0; i < buffers; i++) {
-		OUT_BATCH(i << VB0_BUFFER_INDEX_SHIFT |
+		OUT_BATCH(i << GEN6_VB0_BUFFER_INDEX_SHIFT |
 			  GEN8_VB0_BUFFER_ADDR_MOD_EN);
 		OUT_BATCH(0); /* Address */
 		OUT_BATCH(0);
@@ -180,16 +180,16 @@ static void gen8_emit_vertex_elements(struct intel_batchbuffer *batch)
 	const int elements = 34;
 	int i;
 
-	OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS |
+	OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS |
 		(((2 * elements) + 1) - 2) /* DWORD count - 2 */);
 
 	/* Element 0 */
-	OUT_BATCH(VE0_VALID);
+	OUT_BATCH(GEN6_VE0_VALID);
 	OUT_BATCH(
-		GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
-		GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
-		GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
-		GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+		GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+		GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+		GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+		GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
 	/* Elements 1 -> 33 */
 	for (i = 1; i < elements; i++) {
 		OUT_BATCH(0);
@@ -277,18 +277,18 @@ static void gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer *
 
 static void gen8_emit_primitive(struct intel_batchbuffer *batch)
 {
-        OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
-        OUT_BATCH(4);   /* gen8+ ignore the topology type field */
-        OUT_BATCH(1);   /* vertex count */
-        OUT_BATCH(0);
-        OUT_BATCH(1);   /* single instance */
-        OUT_BATCH(0);   /* start instance location */
-        OUT_BATCH(0);   /* index buffer offset, ignored */
+	OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2));
+	OUT_BATCH(4);   /* gen8+ ignore the topology type field */
+	OUT_BATCH(1);   /* vertex count */
+	OUT_BATCH(0);
+	OUT_BATCH(1);   /* single instance */
+	OUT_BATCH(0);   /* start instance location */
+	OUT_BATCH(0);   /* index buffer offset, ignored */
 }
 
 static void gen9_emit_state_base_address(struct intel_batchbuffer *batch) {
 	const unsigned offset = 0;
-	OUT_BATCH(GEN6_STATE_BASE_ADDRESS |
+	OUT_BATCH(GEN4_STATE_BASE_ADDRESS |
 		(19 - 2) /* DWORD count - 2 */);
 
 	/* general state base address - requires BB address
@@ -414,8 +414,8 @@ void gen9_setup_null_render_state(struct intel_batchbuffer *batch)
 	/* State base addresses */
 	gen9_emit_state_base_address(batch);
 
-	OUT_CMD(GEN6_STATE_SIP, 3);
-	OUT_CMD(GEN6_3DSTATE_DRAWING_RECTANGLE, 4);
+	OUT_CMD(GEN4_STATE_SIP, 3);
+	OUT_CMD(GEN4_3DSTATE_DRAWING_RECTANGLE, 4);
 	OUT_CMD(GEN7_3DSTATE_DEPTH_BUFFER, 8);
 
 	/* Chroma key */