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authorRodrigo Siqueira <rodrigosiqueiramelo@gmail.com>2018-07-07 20:22:52 -0300
committerArkadiusz Hiler <arkadiusz.hiler@intel.com>2018-07-11 15:37:32 +0300
commite19fd5549e9cf603251704117fc64f4068be5016 (patch)
treee56c19487f37041981d6f4ef18226ba05a5bcf9f /tools
parent8d8ebe2ba4610fd5ffeade653b66eeec54781f34 (diff)
Fix comparison that always evaluates to false
This commit fix the GCC warning: warning: bitwise comparison always evaluates to false [-Wtautological-compare] } else if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_DAC_SERIAL) { The first comparison already checks DPLLB_MODE_LVDS, in this sense, the second 'if' condition always will be false. This commit changes the comparison to DPLLB_MODE_DAC_SERIAL. Signed-off-by: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com> Acked-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Diffstat (limited to 'tools')
-rw-r--r--tools/intel_reg_decode.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/tools/intel_reg_decode.c b/tools/intel_reg_decode.c
index f3c7d74a..5a632e09 100644
--- a/tools/intel_reg_decode.c
+++ b/tools/intel_reg_decode.c
@@ -1277,7 +1277,7 @@ DEBUGSTRING(ironlake_debug_pch_dpll)
p2 = "Div 7";
else
p2 = "Div 14";
- } else if ((val & DPLLB_MODE_LVDS) == DPLLB_MODE_DAC_SERIAL) {
+ } else if ((val & DPLLB_MODE_DAC_SERIAL) == DPLLB_MODE_DAC_SERIAL) {
mode = "Non-LVDS";
if (val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
p2 = "Div 5";