diff options
| -rw-r--r-- | lib/instdone.c | 89 | ||||
| -rw-r--r-- | lib/intel_reg.h | 33 |
2 files changed, 102 insertions, 20 deletions
diff --git a/lib/instdone.c b/lib/instdone.c index 05429b4b..d77061fa 100644 --- a/lib/instdone.c +++ b/lib/instdone.c @@ -70,6 +70,68 @@ gen6_instdone2_bit(uint32_t bit, const char *name) add_instdone_bit(GEN6_INSTDONE_2, bit, name); } +static void +init_g965_instdone1(void) +{ + gen4_instdone1_bit(I965_GW_CS_DONE_CR, "GW CS CR"); + gen4_instdone1_bit(I965_SVSM_CS_DONE_CR, "SVSM CS CR"); + gen4_instdone1_bit(I965_SVDW_CS_DONE_CR, "SVDW CS CR"); + gen4_instdone1_bit(I965_SVDR_CS_DONE_CR, "SVDR CS CR"); + gen4_instdone1_bit(I965_SVRW_CS_DONE_CR, "SVRW CS CR"); + gen4_instdone1_bit(I965_SVRR_CS_DONE_CR, "SVRR CS CR"); + gen4_instdone1_bit(I965_SVTW_CS_DONE_CR, "SVTW CS CR"); + gen4_instdone1_bit(I965_MASM_CS_DONE_CR, "MASM CS CR"); + gen4_instdone1_bit(I965_MASF_CS_DONE_CR, "MASF CS CR"); + gen4_instdone1_bit(I965_MAW_CS_DONE_CR, "MAW CS CR"); + gen4_instdone1_bit(I965_EM1_CS_DONE_CR, "EM1 CS CR"); + gen4_instdone1_bit(I965_EM0_CS_DONE_CR, "EM0 CS CR"); + gen4_instdone1_bit(I965_UC1_CS_DONE, "UC1 CS"); + gen4_instdone1_bit(I965_UC0_CS_DONE, "UC0 CS"); + gen4_instdone1_bit(I965_URB_CS_DONE, "URB CS"); + gen4_instdone1_bit(I965_ISC_CS_DONE, "ISC CS"); + gen4_instdone1_bit(I965_CL_CS_DONE, "CL CS"); + gen4_instdone1_bit(I965_GS_CS_DONE, "GS CS"); + gen4_instdone1_bit(I965_VS0_CS_DONE, "VS0 CS"); + gen4_instdone1_bit(I965_VF_CS_DONE, "VF CS"); +} + +static void +init_g4x_instdone1(void) +{ + gen4_instdone1_bit(G4X_BCS_DONE, "BCS"); + gen4_instdone1_bit(G4X_CS_DONE, "CS"); + gen4_instdone1_bit(G4X_MASF_DONE, "MASF"); + gen4_instdone1_bit(G4X_SVDW_DONE, "SVDW"); + gen4_instdone1_bit(G4X_SVDR_DONE, "SVDR"); + gen4_instdone1_bit(G4X_SVRW_DONE, "SVRW"); + gen4_instdone1_bit(G4X_SVRR_DONE, "SVRR"); + gen4_instdone1_bit(G4X_ISC_DONE, "ISC"); + gen4_instdone1_bit(G4X_MT_DONE, "MT"); + gen4_instdone1_bit(G4X_RC_DONE, "RC"); + gen4_instdone1_bit(G4X_DAP_DONE, "DAP"); + gen4_instdone1_bit(G4X_MAWB_DONE, "MAWB"); + gen4_instdone1_bit(G4X_MT_IDLE, "MT idle"); + //gen4_instdone1_bit(G4X_GBLT_BUSY, "GBLT"); + gen4_instdone1_bit(G4X_SVSM_DONE, "SVSM"); + gen4_instdone1_bit(G4X_MASM_DONE, "MASM"); + gen4_instdone1_bit(G4X_QC_DONE, "QC"); + gen4_instdone1_bit(G4X_FL_DONE, "FL"); + gen4_instdone1_bit(G4X_SC_DONE, "SC"); + gen4_instdone1_bit(G4X_DM_DONE, "DM"); + gen4_instdone1_bit(G4X_FT_DONE, "FT"); + gen4_instdone1_bit(G4X_DG_DONE, "DG"); + gen4_instdone1_bit(G4X_SI_DONE, "SI"); + gen4_instdone1_bit(G4X_SO_DONE, "SO"); + gen4_instdone1_bit(G4X_PL_DONE, "PL"); + gen4_instdone1_bit(G4X_WIZ_DONE, "WIZ"); + gen4_instdone1_bit(G4X_URB_DONE, "URB"); + gen4_instdone1_bit(G4X_SF_DONE, "SF"); + gen4_instdone1_bit(G4X_CL_DONE, "CL"); + gen4_instdone1_bit(G4X_GS_DONE, "GS"); + gen4_instdone1_bit(G4X_VS0_DONE, "VS0"); + gen4_instdone1_bit(G4X_VF_DONE, "VF"); +} + void init_instdone_definitions(void) { @@ -173,6 +235,8 @@ init_instdone_definitions(void) gen4_instdone_bit(ILK_AI_DONE, "AI"); gen4_instdone_bit(ILK_AC_DONE, "AC"); gen4_instdone_bit(ILK_AM_DONE, "AM"); + + init_g4x_instdone1(); } else if (IS_965(devid)) { gen4_instdone_bit(I965_ROW_0_EU_0_DONE, "Row 0, EU 0"); gen4_instdone_bit(I965_ROW_0_EU_1_DONE, "Row 0, EU 1"); @@ -204,26 +268,11 @@ init_instdone_definitions(void) gen4_instdone_bit(I965_IC_ROW_1_DONE, "Instruction cache row 1"); gen4_instdone_bit(I965_CP_DONE, "Command Processor"); - gen4_instdone1_bit(I965_GW_CS_DONE_CR, "GW CS CR"); - gen4_instdone1_bit(I965_SVSM_CS_DONE_CR, "SVSM CS CR"); - gen4_instdone1_bit(I965_SVDW_CS_DONE_CR, "SVDW CS CR"); - gen4_instdone1_bit(I965_SVDR_CS_DONE_CR, "SVDR CS CR"); - gen4_instdone1_bit(I965_SVRW_CS_DONE_CR, "SVRW CS CR"); - gen4_instdone1_bit(I965_SVRR_CS_DONE_CR, "SVRR CS CR"); - gen4_instdone1_bit(I965_SVTW_CS_DONE_CR, "SVTW CS CR"); - gen4_instdone1_bit(I965_MASM_CS_DONE_CR, "MASM CS CR"); - gen4_instdone1_bit(I965_MASF_CS_DONE_CR, "MASF CS CR"); - gen4_instdone1_bit(I965_MAW_CS_DONE_CR, "MAW CS CR"); - gen4_instdone1_bit(I965_EM1_CS_DONE_CR, "EM1 CS CR"); - gen4_instdone1_bit(I965_EM0_CS_DONE_CR, "EM0 CS CR"); - gen4_instdone1_bit(I965_UC1_CS_DONE, "UC1 CS"); - gen4_instdone1_bit(I965_UC0_CS_DONE, "UC0 CS"); - gen4_instdone1_bit(I965_URB_CS_DONE, "URB CS"); - gen4_instdone1_bit(I965_ISC_CS_DONE, "ISC CS"); - gen4_instdone1_bit(I965_CL_CS_DONE, "CL CS"); - gen4_instdone1_bit(I965_GS_CS_DONE, "GS CS"); - gen4_instdone1_bit(I965_VS0_CS_DONE, "VS0 CS"); - gen4_instdone1_bit(I965_VF_CS_DONE, "VF CS"); + if (IS_G4X(devid)) { + init_g4x_instdone1(); + } else { + init_g965_instdone1(); + } } else if (IS_9XX(devid)) { gen3_instdone_bit(IDCT_DONE, "IDCT"); gen3_instdone_bit(IQ_DONE, "IQ"); diff --git a/lib/intel_reg.h b/lib/intel_reg.h index 7274a8a0..e864375c 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -560,6 +560,39 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define I965_VS0_CS_DONE (1 << 1) # define I965_VF_CS_DONE (1 << 0) +# define G4X_BCS_DONE (1 << 31) +# define G4X_CS_DONE (1 << 30) +# define G4X_MASF_DONE (1 << 29) +# define G4X_SVDW_DONE (1 << 28) +# define G4X_SVDR_DONE (1 << 27) +# define G4X_SVRW_DONE (1 << 26) +# define G4X_SVRR_DONE (1 << 25) +# define G4X_ISC_DONE (1 << 24) +# define G4X_MT_DONE (1 << 23) +# define G4X_RC_DONE (1 << 22) +# define G4X_DAP_DONE (1 << 21) +# define G4X_MAWB_DONE (1 << 20) +# define G4X_MT_IDLE (1 << 19) +# define G4X_GBLT_BUSY (1 << 18) +# define G4X_SVSM_DONE (1 << 17) +# define G4X_MASM_DONE (1 << 16) +# define G4X_QC_DONE (1 << 15) +# define G4X_FL_DONE (1 << 14) +# define G4X_SC_DONE (1 << 13) +# define G4X_DM_DONE (1 << 12) +# define G4X_FT_DONE (1 << 11) +# define G4X_DG_DONE (1 << 10) +# define G4X_SI_DONE (1 << 9) +# define G4X_SO_DONE (1 << 8) +# define G4X_PL_DONE (1 << 7) +# define G4X_WIZ_DONE (1 << 6) +# define G4X_URB_DONE (1 << 5) +# define G4X_SF_DONE (1 << 4) +# define G4X_CL_DONE (1 << 3) +# define G4X_GS_DONE (1 << 2) +# define G4X_VS0_DONE (1 << 1) +# define G4X_VF_DONE (1 << 0) + #define GEN6_INSTDONE_2 0x207c # define GEN6_GAM_DONE (1 << 31) # define GEN6_CS_DONE (1 << 30) |