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2016-11-30assembler: RSQ is a math functionKristian H. Kristensen
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-11-30assembler: Set 3src options before sourcesKristian H. Kristensen
Setting the 3src sources will assert align16, but that doesn't get set until we call set_instruction_options(). Call that before setting sources. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-06-23assembler/: Fix lex warnings for %empty and %nonassoc.marius vlad
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com> Acked-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30assembler/skl: update the extdesc field for SEND instructionZhao Yakui
The send instruction on gen9 uses the 32bit immediate instead of 6bit immediate for the extended message descriptors. And some bits of SEND instruction are defined as the extdesc field. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30assembler/skl: Add more cache agent for write(...)Zhao Yakui
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30assembler/skl: update read(...)Zhao Yakui
READ(...) is used for Render Target read and Media Block read. But there is no sampler cache agent on gen9. At the same time two message types don't share the same cache agent any more. So a parameter is needed for cache agent. The 2th parameter of read(...) is not used for gen6/gen7/gen8. Hence it is reused as cache agent for SKL as that on ILK. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-05-19assembler: switch the order of swizzle and regtype to match the BNF of the ↵Xiang, Haihao
assembly Fortunately our existing source didn't use swizzle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75631 Tested-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-02-13Assembler/bdw: Remove the unsupported cache agent for WRITE(...)Zhao Yakui
The Sampler/Constant cache is read-only. And it can't be used as the target cache agent of WRITE message. Reviewed-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-02-11assembler: fix condition for printing a warningThomas Wood
Signed-off-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-06assembler/bdw: Update write(...)Xiang, Haihao
write(...) is used for Render Target Write and Media Block Write. The two message types no longer share the same cache agent on GEN8, So a parameter is needed for cache agent. The 4th parameter of write() is used for write commit bit which has been removed since GEN7. Hence we can re-use the 4th parameter as cache agent on GEN8 Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-11-06assembler/bdw: Add the DATA_PORT_CACHE1 shared function for Gen8+Zhao Yakui
This is required to send some messages to data port in GPU shader. For example: media_block_write message. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Add the support of align1 register-indirect addressing mode ↵Zhao Yakui
on Gen8 Otherwise it can't compile the following GPU shader that uses the register-indirect addressing mode. >add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw >add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: SEND instructionXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Small cleanupBen Widawsky
This was originally part of: commit 62298329350b965e4bbfc558e5a4b1b3646742ea Author: Xiang, Haihao <haihao.xiang@intel.com> Date: Wed Aug 14 14:21:16 2013 -0700 assembler: error for the wrong syntax of SEND instruction on GEN6+ I merged that patch separately, but this tiny hunk was leftover. In order to not muck in changing too much history, I am leaving this as a discrete patch, but with the changed commit message Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Check & Refinement Engine messageXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Video Motion Estimation(VME) messageXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Thread Spawn messageXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Data port messageXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Set thread switch for multiple branch instructionsXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Set jip/uip offsets used by flow control instructionsXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Disable mask control for advanced modeXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Set math functionXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Use gen8_set_exec_size() to set the execution sizeDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Preliminary gen8 send & msgtarget supportDamien Lespiau
Still some work needed there, but enough for rendercopy. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Make the validation functions take a brw_program_instructionDamien Lespiau
This allows to use the same functions to validate operands on gen8 for now. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Support some basic gen8 intructionsDamien Lespiau
We should now support alu2 intructions with direct register addressing. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-08-20assembler: Tune the error message for invalid send on gen6+Damien Lespiau
And be a bit more descriptive. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-15assembler: error for the wrong syntax of SEND instruction on GEN6+Xiang, Haihao
predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions predicate SEND execsize dst sendleadreg payload imm32reg instoptions predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions The above four syntaxes are only used on legacy platforms which support implied move from payload to dst. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-05-22assembler: Add support for the SENDC instruction.Matt Turner
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Don't use GL typesDamien Lespiau
sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' assembler/*.[ch] Drop the GL types here, they don't bring anything to the table. For instance, GLuint has no guarantee to be 32 bits, so it does not make too much sense to use it in structure describing hardware tables and opcodes. Of course, some bikeshedding can be applied to use uin32_t instead, I figured that some of the GLuint are used without size constraints, so a sed with uint32_t did not seem the right thing to do. On top of that initial sed, one bothered enough could change the structures with size constraints to actually use uint32_t. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use defines for widthDamien Lespiau
Instead of just using hardcoded numbers or resorting to ffs(). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Merge declared_register's type into the reg structureDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use set_instruction_src1() in sendDamien Lespiau
No reason not to! Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use brw_*() functions for 3-src instructionsDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Introduce set_instruction_saturate()Damien Lespiau
Also simplify the logic that was setting the saturate bit in the math instruction. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Introduce set_intruction_pred_cond()Damien Lespiau
This allow us to factor out the test that checks if, when using both predicates and conditional modifiers, we are using the same flag register. Also get rid of of a FIXME that we are now dealing with (the warning mentioned above). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Introduce set_instruction_opcode()Damien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Isolate all the options in their own structureDamien Lespiau
Like with the predicate fields before, there's no need to use the full instruction to collect the list of options. This allows us to decouple the list of options from a specific instruction encoding. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Unify adding options to the headerDamien Lespiau
Right now we have duplicated code for when the option is the last in the list or not. Put that code in a common function. Interestingly it appears that both sides haven't been kept in sync and that EOT and ACCWRCTRL had limitations on where they had to be in the option list. It's fixed now! Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Gather all predicate data in its own structureDamien Lespiau
Rather than user a full instruction for that. Also use set_instruction_predicate() for a case that coud not be done like that before the refactoring (because everyone now uses the same instruction structure). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Move struct relocation out of relocatable instructionsDamien Lespiau
Now that all instructions (relocatable or not) are struct brw_program_instructions, this means we can move the relocation specific information out the "relocatable instruction" structure. This will allow us to share the relocation information between different types of instructions. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Unify all instructions to be brw_program_instructionsDamien Lespiau
Time to finally unify all instructions on the same structure. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Renamed the instruction field to insnDamien Lespiau
This will be less typing for the refactoring to come (which is use struct brw_program_instruction in gram.y for the type of all the instructions). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use brw_set_src1()Damien Lespiau
Everything is now aligned to be able to use brw_set_src1() in the opcode generation, so use it. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Fix ')' placement in conditionDamien Lespiau
A small typo in the condition. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Cleanup visibility of a few global variables/functionsDamien Lespiau
Not everything has to be exported out the compilation unit. Do a small cleanup pass. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Port the warning and error reporting to warn()/error()Damien Lespiau
This way we ensure to have a single place where these are handled. The immediate benefit is that now line numbers are always printed out, which is quite handy. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use brw_set_src0()Damien Lespiau
Unfortunately, it's all a walk in the park. Both, internal code in the assembler and external shaders (libva) generate registers that trigger assertions in brw_eu_emit.c's brw_validate(). To fix all that I took the option to be able to emit warning with the -W flag but still make the assembler generate the same opcodes. We can fix all this, but it requires validation, something that I cannot do right now. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Add the input filename to the error/warning messagesDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Add a check for when ExecSize and width are 1Damien Lespiau
Another check (that we hit if we try to use brw_set_src0()). Again, protect it with the -W option. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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