summaryrefslogtreecommitdiff
path: root/assembler
AgeCommit message (Collapse)Author
2013-03-04assembler: Use brw_reg in the source operandDamien Lespiau
Last refactoring step in transition to struct brw_reg. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Get rid of src operand's swizzle_setDamien Lespiau
swizzle_set can be derived from the value of swizzle itself, no need for that field. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Consolidate the swizzling configuration on 8 bitsDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Replace struct dst_operand by struct brw_regDamien Lespiau
One more step on the road to replacing all register-like structures by struct brw_reg. Two things in this commit are worth noting: * As we are using more and more brw_reg, a lot of the field-by-field assignments can be replaced by 1 assignment which results is a reduction of code * As the destination horizontal stride is now stored on 2 bits in brw_reg, it's not possible to defer the handling of DEFAULT_DSTREGION (aka (int)-1) when setting the destination operand. It has to be done when parsing the region and resolve_dst_region() is a helper for that task. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Unify the direct and indirect register typeDamien Lespiau
They are all struct brw_reg registers now. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Replace struct indirect_reg by struct brw_regDamien Lespiau
More code simplification can be layered on top of that (by using some brw_* helpers to create registers), that'd be for another commit. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Replace struct direct_reg by struct brw_regDamien Lespiau
More code simplification can be layered on top of that (by using some brw_* helpers to create registers), that'd be for another commit. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Make struct declared_register use struct brw_regDamien Lespiau
It's time to start converting the emission code in gram.y to use libbrw infrastructure. Let's start with using brw_reg for declared register. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Don't expose functions only used in main.cDamien Lespiau
and make then static. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Make sure nobody adds a field back to struct brw_instructionDamien Lespiau
Adding something there will break the library, so we might as check for it. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Don't change the size of opcodes!Damien Lespiau
Until now, the assembler had relocation-related fields added to struct brw_instruction. This changes the size of the structure and break code assuming the opcode structure is really 16 bytes, for instance the emission code in brw_eu_emit.c. With this commit, we build on the infrastructure that slowly emerged in the few previous commits to add a relocatable instruction with the needed fields. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Make explicit that labels are part of the instructions listDamien Lespiau
The output of the parsing is a list of struct brw_program_instruction. These instructions can be either GEN instructions aka struct brw_instruction or labels. To make this more explicit we now have a type to test to determine which instruction we are dealing with. This will also allow to to pull the relocation bits into struct brw_program_instruction instead of having them in the structure representing the opcodes. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Refactor the code adding instructions and labelsDamien Lespiau
Factoring out the code from the grammar will allow us to switch to using brw_compile in a cleaner way. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Make print_instruction() take an instructionDamien Lespiau
No need to use a brw_program_instruction there as a brw_instruction is what you really dump anyway, espcially when the plan is to use brw_compile from Mesa sooner rather than later. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Simplify get_subreg_address()Damien Lespiau
This function can only be called to resolve subreg_nr in direct mode (there is an other function for the indirect case) and it makes no sense to call it with an immediate operand. Express those facts with asserts and simplify the logic. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use subreg_nr to store the address register subregDamien Lespiau
Another step towards using struct brw_reg for source and destination operands. Instead of having a separate field to store the sub register number of the address register in indirect access mode, we can reuse the subreg_nr field that was only used for direct access so far. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Remove the writemask_set field of struct dest_operandDamien Lespiau
writemask_set gets in the way of switching to using struct brw_reg and it's possible to derive it from the writemask value. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Use BRW_WRITEMASK_XYZW instead of the 0xf constantDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Import brw_eu_emit.cDamien Lespiau
Finally importing the meaty brw_eu_emit.c code that emit instructions. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Import brw_eu.cDamien Lespiau
Another step the road of importing Mesa's emission code. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Import brw_eu_compact.cDamien Lespiau
To be able to import brw_eu.c and brw_eu_emit.c later on. This could be used to get the assembler generate compact instructions at some point. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Protect gen4asm.h from multiple inclusionsDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Make an libbrw libraryDamien Lespiau
With the brw_* files imported from mesa. There are still a few things in that library that needs gen4asm.h, for instance the GLuint and GLint types. The hope is that eventually libbrw can be split out in its own directory and shared. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Introduce struct brw_contextDamien Lespiau
A lot of the mesa code use struct brw_context to get the GPU generation and various information. Let's stub this structure and initialize it ourselves to be able to resuse mesa's code untouched. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Remove white space from brw_eu.hDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Import ralloc from MesaDamien Lespiau
This also add a new brw_compat.h that should help maintaining the diff between mesa's version and our as small as possible. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Update the disassembler codeDamien Lespiau
From Mesa. This imports a bit more the of brw_eu* infrastructure (which is going towards the right direction!) from mesa and the update is quite a significant improvement over what we had. I also verified that the changes that were done on the assembler old version of brw_disasm.c were already supported by the Mesa version, and indeed they were. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Remove trailing white space from brw_defines.hDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Import brw_defines.h from MesaDamien Lespiau
Almost identical files now, the diff is: -#include "intel_chipset.h" +#define EX_DESC_SFID_MASK 0xF +#define EX_DESC_EOT_MASK 0x20 Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename BRW_ACCWRCTRL_ACCWRCTRLDamien Lespiau
To a more self-describing define. This hopefully will help its inclusion into Mesa. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Adopt enum brw_message_target from mesaDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Remove trailing white spaces from brw_structs.hDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Adopt brw_structs.h from mesaDamien Lespiau
Finally merge both brw_structs.h from mesa. One detail has risen in that last commit, the msg_control field of data port message descriptors. Mesa's msg_control field is sometimes split with messages-specific fields where the assembler (at least for recent generations) exposes the full msg_control value in the send instruction. As libva's shaders encodes the full msg_control value in its send instructions, I've chosen to not take the split msg_control from mesa. It's absolutely possible to have a patch fixing that divergence at some later point. I've also kept a hack introduced with ironlake to not have to rewrite shaders (that encode msg_control in the text, remember), and thus creates a another difference with Mesa. - GLuint msg_control:3; - GLuint msg_type:3; + GLuint msg_control:4; + GLuint msg_type:2; Once again, I've made sure that re-generating libva's shaders don't show any difference. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename bits3.id and bits3.fdDamien Lespiau
As always, to sync with mesa. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename branch_2_offset to break_contDamien Lespiau
Once again, import the equivalent struct from mesa. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename branch to branch_gen6Damien Lespiau
The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename gen5 DP pixel_scoreboard_clear to last_render_targetDamien Lespiau
The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Remove struct dp_write_gen6 and struct use gen6_dpDamien Lespiau
We ended up with 2 structures that where exactly the same, so just use one, which happens to be the one Mesa has. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename dp_gen7 to gen7_dp and sync it with Mesa'sDamien Lespiau
The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. I had to drop how mesa splits msg_control as the current assembly language gives access the the whole msg_control field. Recompiling the xorg and the intel driver of libva shaders doesn't show any difference in the assembly created. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename dp_gen6 to gen6_dp and sync with Mesa'sDamien Lespiau
The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. I had to drop how mesa splits msg_control as the current assembly language gives access the the whole msg_control field. Recompiling the xorg and the intel driver of libva shaders doesn't show any difference in the assembly created. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename dp_read_gen6 to gen6_dp_sampler_const_cacheDamien Lespiau
The purpose of this commit is to synchronize opcode definitions across the gen4asm assembler and mesa. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Rename three_src_gen6 to da3srcDamien Lespiau
Mesa's brw_structs.h has named/renamed this field to da3src. Sync with them. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Sync brw_instruction's header with mesa'sDamien Lespiau
Two changes there, a field has been renamed and one bit of padding is now used for compressed instructions. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04build: Integrate the merged gen assembler in the build systemDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04bump version to 1.3Xiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2013-03-04Fix typo. "donesn't" -> "doesn't"Homer Hsing
2013-03-04Add the CRE enginee for HSW+Zhao Yakui
This is also for media encoding like VME, which can do the operation of check & refinement. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-03-04Fix JMPI encoding for Haswell.Gwenole Beauchesne
It uses the byte-aligned jump instead of 64-bit units. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-03-04Add initial support for Haswell.Gwenole Beauchesne
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
2013-03-04Allow Gen version decimals.Gwenole Beauchesne
This is preparatory work for Haswell (Gen 7.5). Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-29 05:29:31 +0000