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Engines referred by class and instance are getting more popular,
gem_engine_can_store_dword() should handle the situation.
Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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we have a "class/instance to eb flags" helper but not the
opposite, add it.
Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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There is no guarantee that spinners are and will be implemented
using batches. As we have igt_spin_t, manipulate it through
igt_spin_* functions consistently and hide the batch nature.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Similar to sysfs_path - more explicit more better.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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To control hang detection, we manipulate the i915.reset module
parameter. However, to be nice we should SKIP if we cannot modify the
parameter as opposed to outright FAILing.
References: https://bugs.freedesktop.org/show_bug.cgi?id=108891
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
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We are trying to set reset parameter earlier than checking IGT env.
Let's move it after checking IGT env to avoid setting reset parameter
when hang injection is disabled.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Some setups (e.g. guc and gen10+) can not disable the MI_USER_INTERRUPT
generation and so can not simulate missed interrupts. These tests would
fail, so skip when the kernel reports no tests available.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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An hanging batch is nothing more than a spinning batch that never gets
stopped, so re-use the routines implemented in dummyload.c.
v2: Let caller decide spin loop size
v3: Only use loose loops for hangs (Chris)
v4: No requires
v5: Free the spinner
v6: Chamelium exists.
Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com> #v3
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
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As we ordinarily use a spinning batch to trigger a hang, we cannot do so
without execbuf. On the other hand, if we do a manual reset of the
wedged driver, we expect it to remain wedged and for the reset to fail;
failing the test. Even if we remove the igt_assert(!wedged), the test is
suspect as we don't know if the reset took place and so do not know if
the conditions the test is trying to setup apply.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Pollable spin batch exports a spin->running pointer which can be checked
by dereferencing it to see if the spinner is actually executing on the
GPU.
This is useful for tests which want to make sure they do not proceed with
their next step whilst the spinner is potentially only being processed by
the driver and not actually executing.
Pollable spinner can be created with igt_spin_batch_new_poll or
__igt_spin_batch_new_poll, after which igt_spin_busywait_until_running can
be used to busy wait until it is executing.
v2:
* Move READ_ONCE to igt_core.
* Add igt_spin_busywait_until_running. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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valgrind complains we feed uninitialised stack into the CONTEXT_SETPARAM
ioctl. It is unused by the kernel, but valgrind doesn't know that and
it's easy enough to clear the struct to prevent the warning.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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A couple of bugs inside the hang injector, the worst being that the
presumed_offset of the reloc didn't match the batch; so if the reloc was
skipped (as the presumed_offset matched the reloc offset), the batch
wasn't updated and so we may not have generated a hanging batch at all!
Secondly, the MI_BATCH_BUFFER_START was not correct for all gen.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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We current have a single for_each_engine() iterator which we use to
generate both a set of uABI engines and a set of physical engines.
Determining what uABI ring-id corresponds to an actual HW engine is
tricky, so pull that out to a library function and introduce
for_each_physical_engine() for cases where we want to issue requests
once on each HW ring (avoiding aliasing issues).
v2: Remember can_store_dword for gem_sync
v3: Find more open-coded for_each_physical
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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One weird issue we see in bug 104676 is that the hangs are too fast on
HSW! So force the use of the slow spinners that do not try to trigger
a hang by injecting random bytes into the batch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104676
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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The for_each_engine_class_instance macro stops at e__->name being
NULL, so add an object that is so.
Signed-off-by: Petri Latvala <petri.latvala@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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A bunch of tests for the new i915 PMU feature.
Parts of the code were initialy sketched by Dmitry Rogozhkin.
v2: (Most suggestions by Chris Wilson)
* Add new class/instance based engine list.
* Add gem_has_engine/gem_require_engine to work with class/instance.
* Use the above two throughout the test.
* Shorten tests to 100ms busy batches, seems enough.
* Add queued counter sanity checks.
* Use igt_nsec_elapsed.
* Skip on perf -ENODEV in some tests instead of embedding knowledge locally.
* Fix multi ordering for busy accounting.
* Use new guranteed_usleep when sleep time is asserted on.
* Check for no queued when idle/busy.
* Add queued counter init test.
* Add queued tests.
* Consolidate and increase multiple busy engines tests to most-busy and
all-busy tests.
* Guarantte interrupts by using fences.
* Test RC6 via forcewake.
v3:
* Tweak assert in interrupts subtest.
* Sprinkle of comments.
* Fix multi-client test which got broken in v2.
v4:
* Measured instead of guaranteed sleep.
* Missing sync in no_sema.
* Log busyness before asserts for debug.
* access(2) instead of open(2) to determine if cpu0 is hotpluggable.
* Test frequency reporting via min/max setting instead assuming.
^^ All above suggested by Chris Wilson. ^^
* Drop queued subtests to match i915.
* Use long batches with fences to ensure interrupts.
* Test render node as well.
v5:
* Add to meson build. (Petri Latvala)
* Use 1eN constants. (Chris Wilson)
* Add tests for semaphore and event waiting.
v6:
* Fix interrupts subtest by polling the fence from the "outside".
(Chris Wilson)
v7:
* Assert number of initialized engines matches the expectation.
(Chris Wilson)
* Warn instead of skipping if we couldn't restore the initial
frequency. (Chris Wilson)
* Move all asserts to after the test cleanup (just a tidy).
* More 1eN notation for timeouts.
* Bump the tolerance to 5% since I saw a few noisy runs with
sampling counters.
* Always start the PMU before submitting batches to lower
reliance on i915 doing the delayed engine busy stats disable.
v8:
* Update for upstream engine class enum.
v9:
* Add meson build support.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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The MMAP_V2 is replaced by just using MMAP, since the official header
has the updated struct. The gem_create_v2 and gem_get_aperture are
left as is, because they seem to not be reflected in the UABI header!
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Petri Latvala <petri.latvala@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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We only suppress the error state from the context, iff we trigger the
GPU reset by hangcheck (igt_hang_ring). If we trigger an immediate reset
via igt_force_gpu_reset(), we will populate the error-state but not free
it because we thought we have it suppressed by the context parameter.
Always eat the error after we expect a GPU reset and have not specified
that we want to keep it.
The side-effect of keeping the error-state around after we deliberately
created it is that subsequent GPU hangs are not prominently recorded, as
the kernel believes they are secondary hangs (and we only announce the
first).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
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Since I accidentally broke the build for some, by putting the pretty
printer for submission inside ifdef HAVE_PROCPS, it's time to move the
whole thing into lib/i915 while fixing this mistake.
Let's also rename the pretty printer and add a doc to it as well as the
section.
Fixes: f6dfe556659f ("lib: Extract helpers for determining submission method")
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Couple of tests are using either determining submission method, or
pretty printing. Let's move those to helpers in lib.
v2: s/igt_show/gem_show
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
Acked-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
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This limitation does not exist in latest kernel. It was removed by this patch-
commit f7978a0c581a8a840a28306f8da43e06e7fef3bf
v2: Added commit id that removes the limitation(Chris Wilson)
V3: Generic way to find if kernel supports this instead of hardcoding gens(Chris Wilson)
v4: Optimize the if block (Daniele)
v5: Use the same context instead of creating a dummy (Chris Wilson)
v6: Changed comment structure and removed extra brackets, local var (Chris Wilson)
v7: Removed some more extra brackets
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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The early gen3 machines inherited the MI block and restrictions from
gen2, and may only use physical addresses in conjunction with
MI_STORE_DATA_IMM -- that makes it unusable for us from userspace, where
we can only use virtual offsets.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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The idea behind using an illegal instruction was to hang the GPU must
faster than simply using the recursive batch. However, we stopped doing
so on gen8+ as the CS parser was much laxer and allowed the illegal
command through but still interpreted the packet length (jumping over
the recursive batch buffer start that followed). Sandybridge doesn't
just hang the GPU when it encounters an illegal command on the BLT
engine, it hangs the machine. That goes above and beyond testing our
hangcheck + reset, so remove the deadly instructions.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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This reverts commit d7a0b61450797a3d6644c65aebf75c2a90da1a15.
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Default is not an engine but an ABI alias for RCS. Remove it
from the engine list to eliminate redundant subtests and test
passes.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@intel.com>
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The hang detector relies on a uevent for notification and aborting the
test. As proposed, fine-grained resets may not produce a global uevent
and so this hang detection becomes void. As we don't expect any hang, we
can just reduce the reset to only a global + uevent and so maintain
functionality, and switch back to fine-grained resets afterwards.
Note that any test that requires testing fine-grained resets should
ensure that they are enabled first as igt may leave the global
parameters in an inconsistent state.
v2: Restore fine-grained resets for explict igt_allow_hang()
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
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ffs() was used in couple of places without explicitly including
strings.h. On a few libc implementation this is done implicitly through
other headers, but let's do not rely on that behavior.
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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Rather than have the code in multiple locations, put a copy in lib/
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Another day, another format. Now we include the 0-based instance number
for all engines, and not just vcs1/2.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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As we can export igt_debugfs_dir() to cache the path to our debugfs
directory, encourage a few more users to take advantage.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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This reverts commit 25fbae15262cf570e207e62f50e7c5233e06bc67, restoring
commit 301ad44cdf1b868b1ab89096721da91fa8541fdc
Author: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Date: Thu Mar 2 10:37:11 2017 +0100
lib: Open debugfs files for the given DRM device
with fixes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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This reverts commit 301ad44cdf1b868b1ab89096721da91fa8541fdc.
When a render-only device is opened and gem_quiescent_gpu is called, we
need to use the debugfs dir for the master device instead.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
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When opening a DRM debugfs file, locate the right path based on the
given DRM device FD.
This is needed so, in setups with more than one DRM device, any
operations on debugfs files affect the expected DRM device.
v2: - rebased and fixed new API additions
v3: - updated chamelium test, which was missed previously
- use the minor of the device for the debugfs path, not the major
- have a proper exit handler for calling igt_hpd_storm_reset with the
right device fd.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
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igt_debugfs.c: In function 'igt_drop_caches_has':
igt_debugfs.c:890:9: warning: ignoring return value of 'fscanf', declared with attribute warn_unused_result [-Wunused-result]
fscanf(file, "0x%" PRIx64, &mask);
^
CC igt_aux.lo
CC igt_gt.lo
igt_gt.c: In function 'igt_force_gpu_reset':
igt_gt.c:382:8: warning: ignoring return value of 'fscanf', declared with attribute warn_unused_result [-Wunused-result]
fscanf(file, "%d", &wedged);
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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LOCAL_CONTEXT_PARAM_NO_ERROR_CAPTURE exists in lib/ioctl_wrappers.h
since commit 171b21d9f761 ("igt/gem_ctx_param: Update invalid parma
number").
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Context BAN_PERIOD will get depracated so subsitute it with BANNABLE
property. Make ctx param test to accept both variants for now
until kernel changes have landed, to not break BAT.
v2: check against - EINVAL on get/set ban as it can return -EPERM
v3: better naming for get/set (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
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The stable path is via sys, but we only have to use this should the
kernel be ignoring our request to ignore simulated hangs.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Moved variable declaration inside #if case to avoid unused variable warnings
on non-x86 targets.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
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If the error state just contains the hanging batch, and we are not
verifying the error capture, tell the kernel to ignore it.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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0xffffffff as an illegal command confuses the command execution
on gen9 so that the next BB start will get ignored, causing a runaway
head past the bb end. This delays the hang detection substantially
as hangcheck then observes only a non progressing seqno.
Omit the bad instruction on gen8+ and rely on the chained batch
loop to cause a deterministic hang. Make the chained bb start
to jump straight into bb start, omitting the MI_NOOP or the bad
instruction on subsequent passes. This makes the acthd sampling
to hit more reliably to the same value, as the loop is smaller,
making the head appear to be 'more stuck'.
References: https://bugs.freedesktop.org/show_bug.cgi?id=92715
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
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First try an illegal instruction before the infinite loop to try and
trigger a gpu hang more gracefully as the infinite loop is causing some
older machines issues as the GPU hogs the entire systems and makes the
machine laggy, unresponsive for long periods.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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On Baytrail, Braswell and Atoms beyond we see an issue where the mfence
is insufficient to force the cacheline to be coherent (i.e. such that
writes from the GPU are visible by the CPU after the call to clflush). A
second clflush is ordered with an earlier clflush to the same address
and this appears sufficient to give the coherency required for GPU/CPU
interop.
Testcase: igt/gem_exec_flush
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Akash Goel <akash.goel@intel.com>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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