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We already have the routine we need in drv_suspend. Let's move it to lib
and use it in the mlocking tests. We can also make it a bit faster if we
tweak the initial step and initial amount.
(I think it's safe to assume that we should be able to lock 3/4
of RAM, this cuts the probe time on my 32G SKL - from ~530s to ~180s)
v2: Use available mem, amend step, also lock outside of fork,
early exit if the assumption is wrong (Chris)
Update the function name in doc (Ewelina)
v3: Total for pin, available for initial lock (Chris)
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ewelina Musial <ewelina.musial@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ewelina Musial <ewelina.musial@intel.com>
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All subtests send a workload to the engines and then return without
waiting on it, while this is not a problem because the test targets the
API, it makes the hang detector pointless since the driver will declare
an hang long after the test has completed.
v2:
- Use common functions to create/terminate a batch. (Chris)
Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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As the swizzling is baked into the tiling pattern, the swizzling has to
be consistent across the entire GTT mmap for our tests to work. However,
under L-shaped memory configurations on older architectures, the
swizzling varied depending on which region the page found itself in --
invalidating our assumptions and ability to predict the tiling pattern.
Reported-by: Adric Blake <promarbler14@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106848
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Recently we discovered that we have a race between swapping and
suspend in our resume path (we might be trying to page in an object
after disabling the block devices). Let's try to exercise that by
exhausting all of system memory before suspend.
v2: Explicitly share the large memory area on forking to avoid running
out of memory inside the suspend helpers (for they fork!)
References: https://bugs.freedesktop.org/show_bug.cgi?id=106640
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
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Insted of just trying out each pixel format once, let's try each one
with a set of colors (RGB,CMY,white,black). We'll grab a reference CRC
for each using XRGB8888, and then compare that with the CRC we get
with any other format.
We have to use a solid color fb because chroma subsampling would
generally prevent us from getting a match if we had any color
transitions in the fb contents.
We also abuse the legacy LUT to drop the precision down to 6 bits
so that still errors causes by the RGB<->YCbCr conversion end up
being ignored.
v2: don't set Broadcast RGB prop if it's not there
v3: Drop the Broadcast RGB prop since igt_kms already does it (Maarten)
v4: Don't check ARGB8888 twice on cursors
Add vblank wait after the commit to make sure we grab the crc
for the new fb
Don't turn the plane off between every check
Fix the commit message to say we keep only 6 msbs, 7 is too much
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #v3
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Batches are constrained in their position within the GTT by the kernel,
and if they are in an invalid position will be unbound and rebound
before execution. In our test setup, we therefore need to place the
batch into a valid poistion within the GTT before we fill the ring with
busyspinners.
The problem entirely lies in how we are constructing our set of busy
spinning batches. We try to fill the ring with a chain of batches that
are all linked to one buffer, and then try to execute that buffer. This
gives us the most implicit fences on that one buffer we can trivially
construct; with the goal being that the kernel handles them all with
aplomb. However, what we failed to take into account was that we might
end up with that final buffer being at address 0, which is in an invalid
location to execute from (because reasons) and the kernel would be
forced to move it. However, since we have a ring full of busy spinners
all using that buffer, we can not move that buffer until we wait for the
queue to complete -- which it never will and so we declare a GPU hang,
failing the test.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Add some various test suites relevant for the vc4 drm driver.
Acked-by: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
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glk is failing gem_tiled_blits which is very odd as it doesn't use
fencing and so the tiling is all internal to the GPU. From the small
number of examples seen so far, it looks like just a single bit is being
flipped. Let's dump some values to see if it there is a larger pattern
here.
Furthermore since gem_linear_blits is also showing bitflips on glk, we
can rule out the impact of tiling altogether! It just becomes a question
of which piece of hw is broken...
References: https://bugs.freedesktop.org/show_bug.cgi?id=106608
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
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There is a chance new kernel or new firmware fixed the CPU0 hotplug hang
issue. Remove the skip to check if that's true.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Jani Saarinen <jani.saarinen@intel.com>
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We may not idle immediately after a hang, and indeed may send a pulse
down the pipeline periodically to become idle. Rather than make a flimsy
assumption about how long we need to sleep before the system idles,
wait for the system to declare itself idle; flushing it to idle in the
process!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
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Lionel pointed out that INSTPM was context saved, at least from gen6,
not from gen9. The only caveat is that INSTPM is a masked register (the
upper 16bits are a write-enable mask, the lower 16bits the value to
change) and also contains a read-only counter bit (which counts flushes,
and so flip flops between batches). Being a non-privileged register that
userspace wants to manipulate, it is writable and readable from a
userspace batch, so we can test whether or not a write from one context
is visible from a second.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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As the test notes, DRM_FORMAT_ARGB8888 is broken for CRC comparison,
and should not be used on gen9-gen10.
DRM_FORMAT_C8 failed on my glk, because it was running into the pitch
pixel limit when 4 * width is used. Track bpp correctly, and use it with
igt_get_fb_tile_size to get a more accurate size without reinventing
the wheel.
Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106641
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The legacy test fails because it tries scaling on pipe C,
because the single scaler is already used for CRTC scaling.
On other pipes and newer gens we have 2 scalers, so special
case pipe C here.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105456
[mlankhorst: Add ickles comment.]
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Two tests uses the very same wait_for_pageflip() routine. These tests are
'kms_rotation_crc' and 'kms_flip_tiling'. In order to decrease code
repetition, let's move this function as part of kms function collection
in igt_kms.
No functional changes.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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We can override the connector status/EDID just fine even if the
thing is already connected. So let's not skip in that case.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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The 9x9 was maybe a workaround for the kernel's rounding behaviour?
The kernel was changed so that's no longer necessary. So let's go
for 8x8 since that actually works with YUV formats.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
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YUV formats require the clipped src coordinates to be suitably aligned.
We'd need to very carefully compute the unclipped dst coordinates to
guarantee that. That's too much hassle so let's just accept failure in
case YUV formats are used.
v2: Actually remove the original igt_display_commit2() (Maarten)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
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Clear the igt_fb struct to make sure no stack garbage is left in any
members we don't explicitly initialize.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
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Ask from kernel about supported modes for each plane and try setting
them on display and verify functionality with crc.
DRM_FORMAT_ARGB8888 and DRM_FORMAT_ABGR8888 skip crc testing on
primary and overlay planes because they produce incorrect crcs from
hardware. DRM_FORMAT_ARGB8888 is tested on cursor plane.
v3: address review comments from Mika Kahola.
Stop crc at end of test before freeing it. Use libdrm instead
of mixing ioctl and libdrm.
v2: Address review comments from Mika Kahola.
Keep crc running for all tests while on same pipe, set tile height
to 16 and read only one crc per test.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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The test wrote to the same dwords from multiple contexts, assuming that
the writes would be ordered by its submission. However, as it was using
multiple contexts without a write hazard, those timelines are not
coupled and the requests may be emitted to hw in any order. So emit a
write hazard for each individual dword in the scratch (avoiding the
write hazard for the scratch as a whole) to ensure the writes do occur
in the expected order.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Consistent with other function signatures in the file.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>
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After the initial plane setup, only the test plane is required. One
exception is clean_up where the primary is required, but a call to
igt_output_get_plane_type() can get us that.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>
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Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>
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The CRC values are useful as a reference to compare them with values
generated from other feature (PSR) tests.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>
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The goal of this test is (or should be) to verify DRRS is disabled if PSR
was enabled. There is no point in checking for DRRS status if PSR was not
enabled in the first place.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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No reason for the delay between dpms off and on.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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I don't see a big difference in what {dpms,suspend}_psr_exit and
{dpms_off, suspend}_psr_active tests uniquely achieve. Combine them so
that we have one dpms and one suspend test.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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No PSR event should take 10s, don't see value in this test.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Eliminate three memcpy's and four sscanf's.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Include minor fomatting change too.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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It will be reused to enable PSR debug in the later patches.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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psr_active() checks the debugfs flag "HW Enabled & Active bit", which only
tells us if PSR was enabled by the driver. The state of PSR - active
or inactive is different from this flag for DDI platforms, so rename the
function appropriately.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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And rename psr_drrs to no_drrs.
Makes the name consistent with other tests.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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And rename the function to match what it does.
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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trigger_reset() imposes a tight time constraint (2s) so that we verify
that the reset itself completes quickly. In the middle of this check, we
call gem_quiescent_gpu() which may invoke an rcu_barrier() or two to
clear out the freed memory (DROP_FREED). Those barriers may have
unbounded latency pushing beyond the 2s timeout, so restrict the
operation to only wait-for-idle (DROP_ACTIVE).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105957
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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If we trigger "too many" resets, the context and even the file, will be
banned and subsequent execbufs should fail with -EIO.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Check that the kernel rejects a zero user_size.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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The timeout for PC8+ residency change is lowered to 30s. During testing
the entry always happened in ~10s, so thrice that should be a safe bet.
(active USB keyboard, network and screen, no powertop --auto-tune)
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Martin Peres <martin.peres@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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On some devices BIOS limits possible Package C-states via setting one of
the MSRs. The test now skips if the limit is set to a shallower PC-state
than PC8.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Martin Peres <martin.peres@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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CS flips no longer exist, so the test has become useless.
Other tests like kms_busy already perform some testing
that's gpu agnostic.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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When waiting for a finite batch, all that we require is that the batch
completes. If it takes the full second (or longer) for us to wake up and
notice the completed batch is immaterial, so only assert that we don't
report an infinite timeout afterwards.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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Execute the same batch on each engine and check that the composite fence
across all engines completes only after the batch is completed on every
engine.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
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Our parent is RT, we are not. In theory, we should wait until our parent
has gone to sleep before we are allowed to proceed (we should both be
bound to the same cpu). Double down on this by sleeping in the child
until our parent has written a byte along a pipe().
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Make the property validation more thorough:
- validate property flags
- make sure there's an expected number of values/enums
- make sure the possible values make sense
- make sure the current value makes sense
- actually iterate through all planes/crtc/connectors to
check their properties
- make sure encoders don't expose properties while at it
- check that atomic props aren't exposed to non-atomic clients
Still passes on my ivb. Not tested anything else so far.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
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In the existing ABI, each engine operates its own timeline
(fence.context) and so should execute independently of any other. If we
install a blocker on all other engines, that should not affect execution
on the local engine.
v2: Move the requirements checks from the fixture to subtest so that
the test list is stable (Antonio)
v3: Protect SNB from the evil MI_STORE_DWORD.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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I have a cunning plan to make the vma open/close lazy to cache frequent
reallocations (as buffers are passed between applications, e.g. DRI).
However, this will mean that we will not be immediately closing vma and
so need to tell the kernel to process the idle handlers before checking
for leaks.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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The amdgpu tests in tests/amdgpu got installed directly into
$libexecdir before, but test-list.txt still referred to them as
amdgpu/$testname.
This fixes running scripts/run-tests.sh -l with the install directory
as IGT_TEST_ROOT and, I can imagine, actually running them from
install directory (untested). It also removes one FIXME comment for an
internet point.
Signed-off-by: Petri Latvala <petri.latvala@intel.com>
Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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In investigating the issue with having to force preemption within the
executing ELSP[], we want to trigger preemption between all elements of
that array. To that end, we issue a series of requests with different
priorities to fill the in-flight ELSP[] and then demand preemption into
the middle of that series. One can think of even more complicated
reordering requirements of ELSP[], trying to switch between every
possible combination of permutations. Rather than check all 2 billion
combinations, be content with a few.
v2: Add a different pattern for queued requests. Not only do we need to
inject a request into the middle of a single context with a queue of
different priority contexts, but we also want a queue of different
contexts, as they have different patterns of ELSP[] behaviour.
v3: Fixup the naming clash from copy'n'pasting
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
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Before we start trying to use userptr to test interoperability with
PRIME, we first need to check that the device in question has userptr
support.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106013
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Depending on the default mode size, some tests will fail because it
will exceed the maximum size that hardware tracking can handle,
mostly because hardware tracking do not take in care the X and Y
offsets, so the plane size + offsets needs be smaller or equal to
hardware tracking limmits.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105680
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
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