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One significant usecase for intel_reg/etc. is to be able to examine
the hardware state *before* loading the driver. If the tool forces
the driver to load we've totally lost that capability.
This reverts commit 8ae86621d6fff60b6e20c6b0f9b336785c935b0f.
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Michał Winiarski <michal.winiarski@intel.com>
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It allows us to make things a little bit more generic. Also, we now
require fd rather than doing guesswork when it comes to pci address.
v2: Use readlinkat rather than string concat, move stuff around, provide
a version that does not assert. (Chris)
v3: Print addr on failure, avoid assignment in conditionals. (Chris)
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Add 64bit ptes and 8MB mmiobar offset for gen8
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
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With the header cleanup we can now give this header a suitable name,
since it now really only contains register access and other I/O
functions and assorted definitions.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Only include what the header itself needs. The big fish here is
intel-gpu-tools.h. More will follow.
One ugly thing removed here is the duplicated GEN6_TD_CTL #define, one
of which was broken.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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The tool formerly only dumped the aperture size, which is fine, but not
everything interesting. Most of the patch is just the variable rename.
The real work happens with using the BAR0 size divided by 2 instead of
the BAR2 size.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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./tools/intel_gtt -d | head
GTT offset | PTEs
--------------------------------------------------------
0x000000 | 0xe4005015 0xe2854015 0xe283e015 0xe283f015
0x004000 | 0xe28ba015 0xe28bb015 0xe28b6015 0xe28b7015
0x008000 | 0xe2828015 0xe2829015 0xe282a015 0xe282b015
0x00c000 | 0xe2928015 0xe2929015 0xe292a015 0xe292b015
0x010000 | 0xe2918015 0xe2919015 0xe291a015 0xe291b015
0x014000 | 0xe291c015 0xe291d015 0xe291e015 0xe291f015
0x018000 | 0xe2920015 0xe2921015 0xe2922015 0xe2923015
0x01c000 | 0xe2924015 0xe2925015 0xe2926015 0xe2927015
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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This finishes the objective in the last patch which was to actually deal
with physical addresses, and not the PTEs.
GEN6+ Provided support for physical addresses above 4GB. I'm not
actually sure what Ironlake supported, and don't feel like firing up the
timemachine.
v2: Add support for gen4, gen5, and haswell.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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The GTT PTEs that the tool is trying to compare is really about
addresses, and not the PTE itself. To accomplish this, make which
calculates the physical address we actually want.
This commit itself doesn't change any functionality; just the wording in
the code.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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Vincent sent me a patch which I think didn't go far enough.
Honestly, I don't even know what this tool does.
Reported-by: Cheah, Vincent Beng Keat <vincent.beng.keat.cheah@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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Rather than use the common mmio segment which will be in future
restricted to just the registers and so exclude the GTT portion on all
architectures, explicitly mmap the GTT ourselves. Repeat this mmapping
with a couple of flags until we matching the existing kernel mapping.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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... and test for what we mean instead.
Reported-by: Diego Celix <dcelix@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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This is vital in a multi-GPU system so that we only test the Intel card
and not the discrete GPUs.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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A few of the tools can be performed post-mortem from a different system,
so it is useful to be able to compile those tools on those foreign
systems. Obviously, any program to interact with the PCI device or talk
to GEM will fail on a non-Intel system.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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We've used it several times in bringing up the AGP driver, so it seems
useful to have aronud.
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