1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
|
/*
* Copyright © 2011,2012 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Chris Wilson <chris@chris-wilson.co.uk>
* Daniel Vetter <daniel.vetter@ffwll.ch>
*
*/
/*
* Testcase: Check whether we correctly invalidate the cs tlb
*
* Motivated by a strange bug on launchpad where *acth != ipehr, on snb notably
* where everything should be coherent by default.
*
* https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252
*/
#include "igt.h"
#include <unistd.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
#include <drm.h>
IGT_TEST_DESCRIPTION("Check whether we correctly invalidate the cs tlb.");
#define LOCAL_I915_EXEC_VEBOX (4<<0)
#define EXEC_OBJECT_PINNED (1<<4)
#define BATCH_SIZE (1024*1024)
static bool has_softpin(int fd)
{
struct drm_i915_getparam gp;
int val = 0;
memset(&gp, 0, sizeof(gp));
gp.param = 37; /* I915_PARAM_HAS_EXEC_SOFTPIN */
gp.value = &val;
if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp))
return 0;
errno = 0;
return (val == 1);
}
static void *
mmap_coherent(int fd, uint32_t handle, int size)
{
int domain;
void *ptr;
if (gem_has_llc(fd) || !gem_mmap__has_wc(fd)) {
domain = I915_GEM_DOMAIN_CPU;
ptr = gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
} else {
domain = I915_GEM_DOMAIN_WC;
ptr = gem_mmap__wc(fd, handle, 0, size, PROT_WRITE);
}
gem_set_domain(fd, handle, domain, domain);
return ptr;
}
static void run_on_ring(int fd, unsigned ring_id, const char *ring_name)
{
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 execobj;
struct {
uint32_t handle;
uint32_t *batch;
} obj[2];
unsigned i;
char buf[100];
gem_require_ring(fd, ring_id);
igt_require(has_softpin(fd));
for (i = 0; i < 2; i++) {
obj[i].handle = gem_create(fd, BATCH_SIZE);
obj[i].batch = mmap_coherent(fd, obj[i].handle, BATCH_SIZE);
memset(obj[i].batch, 0xff, BATCH_SIZE);
}
memset(&execobj, 0, sizeof(execobj));
execobj.handle = obj[0].handle;
obj[0].batch[0] = MI_BATCH_BUFFER_END;
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(&execobj);
execbuf.buffer_count = 1;
execbuf.flags = ring_id;
/* Execute once to allocate a gtt-offset */
gem_execbuf(fd, &execbuf);
execobj.flags = EXEC_OBJECT_PINNED;
sprintf(buf, "Testing %s cs tlb coherency: ", ring_name);
for (i = 0; i < BATCH_SIZE/64; i++) {
execobj.handle = obj[i&1].handle;
obj[i&1].batch[i*64/4] = MI_BATCH_BUFFER_END;
execbuf.batch_start_offset = i*64;
gem_execbuf(fd, &execbuf);
}
for (i = 0; i < 2; i++) {
gem_close(fd, obj[i].handle);
munmap(obj[i].batch, BATCH_SIZE);
}
}
igt_main
{
const struct intel_execution_engine *e;
int fd = -1;
igt_skip_on_simulation();
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
}
for (e = intel_execution_engines; e->name; e++)
igt_subtest_f("%s%s", e->exec_id ? "" : "basic-", e->name)
run_on_ring(fd, e->exec_id | e->flags, e->name);
igt_fixture
close(fd);
}
|
