diff options
| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-09-01 08:16:42 +0100 |
|---|---|---|
| committer | Andy Green <andy.green@linaro.org> | 2011-09-01 08:16:42 +0100 |
| commit | 19a63ba5a43b026d79ccc526a5c5efc20f3006f1 (patch) | |
| tree | 2934819454b1a47818de9ee90d37f74965245578 | |
| parent | 46a0c106324bb4ee720353ab6bea19e954448385 (diff) | |
OMAP: DSS2: HDMI: change regn definition
regn divider is currently programmed to the registers without change,
but when calculating clock frequencies it is used as regn+1.
To make this similar to how DSI handles the dividers this patch changes
the regn value to be used as such for calculations, but the value
programmed to registers is regn-1.
This simplifies the clock frequency calculations, makes it similar to
DSI, and also allows us to use regn value 0 as undefined.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| -rw-r--r-- | drivers/video/omap2/dss/hdmi.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index 89a84033d0a..064838f41d9 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -41,7 +41,7 @@ #include "dss_features.h" #include <plat/edid.h> -#define HDMI_DEFAULT_REGN 15 +#define HDMI_DEFAULT_REGN 16 #define HDMI_DEFAULT_REGM2 1 static struct { @@ -185,7 +185,7 @@ static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq, r = hdmi_read_reg(PLLCTRL_CFG1); r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ - r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */ + r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */ hdmi_write_reg(PLLCTRL_CFG1, r); @@ -988,7 +988,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, else pi->regn = dssdev->clocks.hdmi.regn; - refclk = clkin / (pi->regn + 1); + refclk = clkin / pi->regn; /* * multiplier is pixel_clk/ref_clk @@ -1014,7 +1014,7 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, * is greater than 1000MHz */ pi->dcofreq = phy > 1000 * 100; - pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10; + pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); |